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Volumn 2003-January, Issue , 2003, Pages 113-118

Code generation for functional validation of pipelined microprocessors

Author keywords

Conferences; Microprocessors; Testing

Indexed keywords

MICROPROCESSOR CHIPS; TEST FACILITIES; TESTING;

EID: 84942905068     PISSN: 15301877     EISSN: 15581780     Source Type: Conference Proceeding    
DOI: 10.1109/ETW.2003.1231677     Document Type: Conference Paper
Times cited : (5)

References (12)
  • 2
    • 0348120352 scopus 로고    scopus 로고
    • Automatic verification of in-order execution in microprocessors with fragmented pipelines and multicycle functional units
    • P. Mishra, H. Tomiyama, N. Dutt, A. Nicolau, "Automatic verification of in-order execution in microprocessors with fragmented pipelines and multicycle functional units", DATE: IEEE Design, Automation & Test in Europe, 2002, pp. 36-43
    • (2002) DATE: IEEE Design, Automation & Test in Europe , pp. 36-43
    • Mishra, P.1    Tomiyama, H.2    Dutt, N.3    Nicolau, A.4
  • 5
    • 0034997102 scopus 로고    scopus 로고
    • Methodology for synthesis, testing, and verification of pipelined architecture processors from behavioral-level-only HDL code and a case study example
    • J. R. Heath, S. Durbha, "Methodology for synthesis, testing, and verification of pipelined architecture processors from behavioral-level-only HDL code and a case study example", Proc. IEEE SoutheastCon, 2001, pp. 143-149
    • Proc. IEEE SoutheastCon, 2001 , pp. 143-149
    • Heath, J.R.1    Durbha, S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.