Methodology for synthesis, testing, and verification of pipelined architecture processors from behavioral-level-only HDL code and a case study example

Conference Proceedings - IEEE SOUTHEASTCON

Volumn , Issue , 2001, Pages 143-149

  Heath, J Robert ^a   Durbha, Sreenivas ^a  

^a UNIVERSITY OF KENTUCKY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS; PERSONAL COMPUTERS; RAPID PROTOTYPING; RESPONSE TIME (COMPUTER SYSTEMS);

CYCLE TIME; HIGH LEVEL DESIGN CODE; PIPELINE ARCHITECTURE PROCESSORS;

PIPELINE PROCESSING SYSTEMS;

EID: 0034997102     PISSN: 07347502     EISSN: None     Source Type: Journal    
DOI: 10.1109/SECON.2001.923104     Document Type: Article

References (0)