On the test of microprocessor IP cores

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2001, Pages 209-213

  Corno, F ^a   Sonza Reorda, M ^a   Squillero, G ^a   Violante, M ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

EFFECTIVE PROGRAMS; FUNCTIONAL APPROACH; IP CORE; MICROPROCESSOR CORE; PRODUCTION PROCESS; SELF-TEST; TEST PROGRAM;

AUTOMATION; EXHIBITIONS;

MICROPROCESSOR CHIPS;

EID: 84893681164     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2001.915026     Document Type: Conference Paper

References (7)

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2. L. Chen, S. Dey, "DEFUSE: A Deterministic Functional Self-Test Methodology for Processors", IEEE VLSI Test Symposium, 2000, pp. 255-262
3. K. Batcher, C. Papachristou, "Instruction Randomization Self Test For Processor Cores", Proc. IEEE VLSI Test Symposium, 1999, pp. 34-40
4. C. A. Papachristou, F. Martin, M. Nourani, "Microprocessor Based Testing for Core-Based System on Chip", ACM/IEEE Design Automation Conf., 1999, pp. 586-591
5. T. M. Niermann, W.-T. Cheng, J. H. Patel, "PROOFS: A Fast, Memory-Efficient Sequential Circuit Fault Simulator", IEEE Trans, on CAD/ICAS, Vol. 11, No. 2, February 1992, pp. 198-207
6. th Design Automation Conference, 1999, pp. 169-174
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