Reconfigurable architecture for autonomous self-repair

IEEE Design and Test of Computers

Volumn 21, Issue 3, 2004, Pages 228-240

  Mitra, Subhasish ^a,b   Huang, Wei Je ^b,c   Saxena, Nirmal R ^b,d   Yu, Shu Yi ^b   McCluskey, Edward J ^b  

^a INTEL CORPORATION   (United States)

^b Stanford University   (United States)

^c NVIDIA   (United States)

^d Alliance Semiconductor ^*  (India)

Author keywords

[No Author keywords available]

Indexed keywords

AUTONOMOUS SELF-REPAIR; BUILT-IN ERROR DETECTION; CONFIGURABLE LOGIC BLOCK; ONLINE ERROR DETECTION;

COMPUTATIONAL METHODS; ERROR DETECTION; FIELD PROGRAMMABLE GATE ARRAYS; MICROPROCESSOR CHIPS; ONLINE SEARCHING; STATIC RANDOM ACCESS STORAGE; TABLE LOOKUP;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 3042668948     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2004.18     Document Type: Article

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