Fast run-time fault location in dependable FPGA-based applications

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2001, Pages 206-214

  Huang, W J ^a   Mitra, S ^a   McCluskey, E J ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AVAILABILITY; COMPUTER SYSTEM RECOVERY; ERROR DETECTION; FAULT TOLERANT COMPUTER SYSTEMS; OPTIMIZATION;

CONCURRENT ERROR DETECTION; FAULT LOCATION;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0035193793     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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