-
1
-
-
0014617202
-
Radiation induced integrated circuit latchup
-
Dec.
-
J.F. Leavy, and R.A. Poll, "Radiation Induced Integrated Circuit Latchup," IEEE Trans. On Nuclear Science, NS-16, Dec. 1969, pp. 96-103.
-
(1969)
IEEE Trans. On Nuclear Science
, vol.NS-16
, pp. 96-103
-
-
Leavy, J.F.1
Poll, R.A.2
-
2
-
-
0014617233
-
Transient radiation response of complementary symmetry MOS integrated circuits
-
December
-
W.J. Dennehy, A. G. Holmes-Seidle, and W.F. Leipold, "Transient Radiation Response of Complementary Symmetry MOS Integrated Circuits," IEEE Trans. On Nuclear Science, NS-16, December 1969, pp. 114-119.
-
(1969)
IEEE Trans. On Nuclear Science
, vol.NS-16
, pp. 114-119
-
-
Dennehy, W.J.1
Holmes-Seidle, A.G.2
Leipold, W.F.3
-
3
-
-
0015770573
-
Latchup in CMOS integrated circuits
-
Dec.
-
B.L. Gregory, and B.D. Shafer, "Latchup in CMOS Integrated Circuits," IEEE Trans. On Nuclear Science, NS-20, Dec. 1973, pp.293-299.
-
(1973)
IEEE Trans. On Nuclear Science
, vol.NS-20
, pp. 293-299
-
-
Gregory, B.L.1
Shafer, B.D.2
-
4
-
-
3042650325
-
CMOS latchup and prevention
-
Alburquerque, MM, June
-
B.L. Gregory, "CMOS Latchup and Prevention," Sandia Laboratories Report SAND75-0371, Alburquerque, MM, June 1975.
-
(1975)
Sandia Laboratories Report
, vol.SAND75-0371
-
-
Gregory, B.L.1
-
5
-
-
1242331678
-
Latchup prevention in CMOS
-
Alburquerque, NM
-
C.E. Barnes, et al, "Latchup Prevention in CMOS," Sandia Laboratory Report SAND76-0048, Alburquerque, NM, 1976.
-
(1976)
Sandia Laboratory Report
, vol.SAND76-0048
-
-
Barnes, C.E.1
-
6
-
-
0037691091
-
Analysis of latchup prevention in CMOS IC's using epitaxial buried layer process
-
D. B. Estreich, A. Ochoa, and R.W. Dutton, "Analysis of Latchup Prevention in CMOS IC's Using Epitaxial Buried Layer Process," in International Electron Device (IEDM) Technical Digest, 1978, pp.230-234.
-
(1978)
International Electron Device (IEDM) Technical Digest
, pp. 230-234
-
-
Estreich, D.B.1
Ochoa, A.2
Dutton, R.W.3
-
8
-
-
0020909950
-
Epitaxial layer enhancement of n-well guard rings for CMOS Circuits
-
Dec.
-
R. Troutman "Epitaxial Layer Enhancement of N-Well Guard Rings for CMOS Circuits," in IEEE Trans. On Elec. Dev. Letters, Vol ED-4, Dec. 1983, pp.438-440.
-
(1983)
IEEE Trans. On Elec. Dev. Letters
, vol.ED-4
, pp. 438-440
-
-
Troutman, R.1
-
10
-
-
0020891350
-
Latchup immunity against noise pulses in a CMOS double well structure
-
Dec.
-
G. Goto, H. Takahashi, and T. Nakamura, "Latchup Immunity Against Noise Pulses in a CMOS Double Well Structure," in International Electron Device Meeting (IEDM) Technical Digest, Dec. 1983, pp. 168-171.
-
(1983)
International Electron Device Meeting (IEDM) Technical Digest
, pp. 168-171
-
-
Goto, G.1
Takahashi, H.2
Nakamura, T.3
-
11
-
-
0020879244
-
Comparison of Latch-up in P- and N-well CMOS circuits
-
December
-
D. Takacs, J. Harter, E.P. Jacobs, C.Werner, U. Schwabe et al, "Comparison of Latch-up in P- and N-well CMOS circuits" in International Electron Device Meeting (IEDM) Technical Digest, December 1983, pp.159-163.
-
(1983)
International Electron Device Meeting (IEDM) Technical Digest
, pp. 159-163
-
-
Takacs, D.1
Harter, J.2
Jacobs, E.P.3
Werner, C.4
Schwabe, U.5
-
12
-
-
0021204461
-
A better understanding of CMOS latchup
-
Jan.
-
G. Hu, "A Better Understanding of CMOS Latchup," in IEEE Trans. Elec. Dev. ED-31, pp. 62-67, Jan. 1984.
-
(1984)
IEEE Trans. Elec. Dev.
, vol.ED-31
, pp. 62-67
-
-
Hu, G.1
-
13
-
-
0022757469
-
Transmission line modeling of substrate resistance and CMOS latchup
-
July
-
R. R. Troutman and M.J. Hargrove, "Transmission Line Modeling of Substrate Resistance and CMOS Latchup," IEEE Trans. Elec. Dev., July 1986.
-
(1986)
IEEE Trans. Elec. Dev.
-
-
Troutman, R.R.1
Hargrove, M.J.2
-
14
-
-
28744434587
-
Retrograde well and epitaxial thickness optimization for shallow- and deep-trench collar merged isolation and node Trench SPT cell and CMOS Logic Technology
-
S. Voldman, M. Marceau, A. Baker, E. Adler, S. Geissler, J. Slinkman, J. Johnson, and M. Paggi, "Retrograde well and epitaxial thickness optimization for shallow- and deep-trench collar merged isolation and node Trench SPT cell and CMOS Logic Technology," in International Electron Device Meeting (IEDM) Technical Digest, 1992, pp.811-815.
-
(1992)
International Electron Device Meeting (IEDM) Technical Digest
, pp. 811-815
-
-
Voldman, S.1
Marceau, M.2
Baker, A.3
Adler, E.4
Geissler, S.5
Slinkman, J.6
Johnson, J.7
Paggi, M.8
-
16
-
-
0029405952
-
MeV implants boost device design
-
Nov.
-
S. Voldman, "MeV Implants Boost Device Design," IEEE Circuits and Devices, Vol. 11, No. 6, Nov. 1995, pp.8-16.
-
(1995)
IEEE Circuits and Devices
, vol.11
, Issue.6
, pp. 8-16
-
-
Voldman, S.1
-
17
-
-
0031707249
-
Latchup in CMOS
-
Invited Talk, April
-
M. Hargrove, S. Voldman, J. Brown, K. Duncan, and W. Craig, "Latchup in CMOS," Invited Talk, in Proceedings of the International Reliability Physics Symposium, April 1998, pp.269-278.
-
(1998)
Proceedings of the International Reliability Physics Symposium
, pp. 269-278
-
-
Hargrove, M.1
Voldman, S.2
Brown, J.3
Duncan, K.4
Craig, W.5
-
18
-
-
3042603749
-
CMOS latchup
-
Invited Talk, Latchup Session, May
-
W. Morris, "CMOS Latchup," Invited Talk, Latchup Session, in Proceedings of the International Reliability Physics Symposium, May 2003, pp.86-74.
-
(2003)
Proceedings of the International Reliability Physics Symposium
, pp. 86-74
-
-
Morris, W.1
-
19
-
-
0038649271
-
A Transmission Line Pulse (TLP) Picosecond Imaging Circuit Analysis (PICA) Methodology for Evaluation of ESD and latchup
-
Latchup Session, May
-
A. Weger, S. Voldman, F. Stellari, P. Song, P. Sanda, and M. McManus, "A Transmission Line Pulse (TLP) Picosecond Imaging Circuit Analysis (PICA) Methodology for Evaluation of ESD and Latchup," Latchup Session, in Proceedings of the International Reliability Physics Symposium, May 2003, pp. 99-104.
-
(2003)
Proceedings of the International Reliability Physics Symposium
, pp. 99-104
-
-
Weger, A.1
Voldman, S.2
Stellari, F.3
Song, P.4
Sanda, P.5
McManus, M.6
-
20
-
-
0038310272
-
A new I/O signal latchup phenomenon in voltage tolerance ESD protection circuits
-
Latchup Sesssion, May
-
J. Salcedo-Suner, R. Cline, C. Duvvury, A. Cadena-Hernandez, L. Ting, and J. Schichl, "A new I/O signal latchup phenomenon in voltage tolerance ESD protection circuits," Latchup Sesssion, in Proceedings of the International Reliability Physics Symposium, May 2003, pp. 85-92.
-
(2003)
Proceedings of the International Reliability Physics Symposium
, pp. 85-92
-
-
Salcedo-Suner, J.1
Cline, R.2
Duvvury, C.3
Cadena-Hernandez, A.4
Ting, L.5
Schichl, J.6
-
21
-
-
0037634701
-
New observance and analysis of various guard ring structures on latchup-hardness by backside photo emission image
-
Latchup Session, May
-
S. Liao, C. Niou, W.T.K. Chien, A. Guo, W. Dong, and C. Huang, "New Observance and Analysis of Various Guard Ring Structures on Latchup-Hardness by Backside Photo emission Image," Latchup Session, in Proceedings of the International Reliability Physics Symposium, May 2003, pp.92-99.
-
(2003)
Proceedings of the International Reliability Physics Symposium
, pp. 92-99
-
-
Liao, S.1
Niou, C.2
Chien, W.T.K.3
Guo, A.4
Dong, W.5
Huang, C.6
-
22
-
-
0003390977
-
Effects of intrinsic gettering on RAM corruption and device yield of a CMOS process
-
L. A. Cerra and H. Chiou, "Effects of intrinsic gettering on RAM corruption and device yield of a CMOS process," in Semiconductor Silicon, Electrochemical Society, p. 884, 1994.
-
(1994)
Semiconductor Silicon, Electrochemical Society
, pp. 884
-
-
Cerra, L.A.1
Chiou, H.2
-
23
-
-
0022688383
-
Device characteristics of MOSFETs in MeV implanted substrates
-
March
-
H. P. Zappe, and C. Hu, "Device characteristics of MOSFETs in MeV implanted substrates," in Nuclear Instrumentation Methods Physical Review, Vol. B21, March 1987, pp. 163-167.
-
(1987)
Nuclear Instrumentation Methods Physical Review
, vol.B21
, pp. 163-167
-
-
Zappe, H.P.1
Hu, C.2
-
24
-
-
0003321112
-
High Energy Implantation for profiled tub formation and impurity gettering in deep submicron CMOS technology
-
March
-
D. C. Jacobson et. al., "High Energy Implantation for profiled tub formation and impurity gettering in deep submicron CMOS technology," in Nuclear Instrumentation Methods Phys. Review, Vol. B96, March 1995, pp. 416-419.
-
(1995)
Nuclear Instrumentation Methods Phys. Review
, vol.B96
, pp. 416-419
-
-
Jacobson, D.C.1
-
25
-
-
0024607604
-
Improvements of CMOS latchup using a high energy buried layer
-
March
-
H. Y. Lin, and C. H. Ting, "Improvements of CMOS latchup using a high energy buried layer," Nuclear Instrumentation Methods Phys. Review, Vol. B38/39, March 1989, pp. 960-964.
-
(1989)
Nuclear Instrumentation Methods Phys. Review
, vol.B38
, Issue.39
, pp. 960-964
-
-
Lin, H.Y.1
Ting, C.H.2
-
27
-
-
0025578736
-
Self gettering and proximity gettering for buried layer formation by MeV ion implantation
-
Dec.
-
T. Kuroi, S. Komori, H. Miyatake, and K. Tsukamoto, "Self gettering and proximity gettering for buried layer formation by MeV ion implantation," in International Electron Device Meeting (IEDM) Technical Digest, Dec. 1990, pp. 261-264.
-
(1990)
International Electron Device Meeting (IEDM) Technical Digest
, pp. 261-264
-
-
Kuroi, T.1
Komori, S.2
Miyatake, H.3
Tsukamoto, K.4
-
28
-
-
0001552583
-
Iron gettering mechanisms in silicon
-
Sept.
-
J. L. Benton et. al., "Iron gettering mechanisms in silicon," J. Applied Physics, Vol. 80, Sept. 1996, pp. 3275-3284.
-
(1996)
J. Applied Physics
, vol.80
, pp. 3275-3284
-
-
Benton, J.L.1
-
29
-
-
0001001458
-
Formation of extended defects in silicon by high energy implantation of B and P
-
August
-
J. Y. Cheng et al, "Formation of extended defects in silicon by high energy implantation of B and P," Journal of Applied Physics, Vol. 80, August 1996, pp. 2105-2112.
-
(1996)
Journal of Applied Physics
, vol.80
, pp. 2105-2112
-
-
Cheng, J.Y.1
-
31
-
-
0000618496
-
The effect of as-implanted damage on the microstructure of threading dislocations in MeV implanted silicon
-
August, August 1999
-
K. K. Bourdelle, D. J. Eaglesham, D. C. Jacobson, and J. Poate, "The effect of as-implanted damage on the microstructure of threading dislocations in MeV implanted silicon," Jour. of Applied Physics, Vol. 86, August 1999, August 1999, pp. 1221-1225.
-
(1999)
Jour. of Applied Physics
, vol.86
, pp. 1221-1225
-
-
Bourdelle, K.K.1
Eaglesham, D.J.2
Jacobson, D.C.3
Poate, J.4
-
32
-
-
78649876234
-
Epi-replacement in CMOS technology by high dose, high energy boron implantation into Cz substrates
-
K. K Bourdelle, Y. Chen, R. Ashton, L. Rubin, A. Agarwal, and W. Morris, "Epi-Replacement in CMOS Technology by High Dose, High Energy Boron Implantation into Cz Substrates," in Intenational Electron Device Meeting (IEDM) Technical Digest, pp. 312-316.
-
Intenational Electron Device Meeting (IEDM) Technical Digest
, pp. 312-316
-
-
Bourdelle, K.K.1
Chen, Y.2
Ashton, R.3
Rubin, L.4
Agarwal, A.5
Morris, W.6
-
33
-
-
3042603747
-
Deep trench guard ring structures and evaluation of the probability of minority carrier escape for ESD and latchup in advanced BiCMOS SiGe technology
-
National Chiao-Tung University, Hsin-chu City, Taiwan, November 12-13
-
A. Watson, S. Voldman, and T. Larsen, "Deep Trench Guard Ring Structures and Evaluation of the Probability of Minority Carrier Escape for ESD and Latchup in Advanced BiCMOS SiGe Technology," in Proceedings of the Taiwan Electrostatic Discharge Conference, National Chiao-Tung University, Hsin-chu City, Taiwan, November 12-13, 2003, pp. 97-103.
-
(2003)
Proceedings of the Taiwan Electrostatic Discharge Conference
, pp. 97-103
-
-
Watson, A.1
Voldman, S.2
Larsen, T.3
-
34
-
-
84945207434
-
The effect of deep trench isolation, trench isolation, and sub-collector on the Electrostatic Discharge (ESD) robustness of Radio Frequency (RF) ESD STI-bound P+/N-well diodes in a BiCMOS silicon germanium technology
-
Sept.
-
th EOS/ESD Symposium, Sept. 2003, pp. 214-223.
-
(2003)
th EOS/ESD Symposium
, pp. 214-223
-
-
Voldman, S.1
-
35
-
-
0037972719
-
Investigation of ESD devices in 0.18 um SiGe BiCMOS process
-
May
-
S.S. Chen, T.Y. Chen, T. H. Tang, T. L. Hsu, H.C. Tseng, J.K. Chen, and C. H. Chou, "Investigation of ESD devices in 0.18 um SiGe BiCMOS process," in Proceedings of the International Reliability Physics Symposium, May 2003, pp. 357-361.
-
(2003)
Proceedings of the International Reliability Physics Symposium
, pp. 357-361
-
-
Chen, S.S.1
Chen, T.Y.2
Tang, T.H.3
Hsu, T.L.4
Tseng, H.C.5
Chen, J.K.6
Chou, C.H.7
-
36
-
-
0038649035
-
The influence of process and design of sub-collectors on the BSD robustness of ESD structures and silicon germanium heterojunction bipolar transistors in a BiCMOS SiGe technology
-
May
-
S. Voldman, L. Lanzerotti, B. Ronan, S. St Onge, and J. Dunn, "The influence of process and design of sub-collectors on the BSD robustness of ESD structures and silicon germanium heterojunction bipolar transistors in a BiCMOS SiGe technology," in Proceedings of the International Reliability Physics Symposium, May 2003, pp. 347-356.
-
(2003)
Proceedings of the International Reliability Physics Symposium
, pp. 347-356
-
-
Voldman, S.1
Lanzerotti, L.2
Ronan, B.3
Onge, S.St.4
Dunn, J.5
-
37
-
-
84932172203
-
The influence of deep trench and substrate resistance on the latchup robustness in a BiCMOS silicon germanium technology
-
April 25-27
-
S. Voldman, and A. Watson, "The Influence of Deep Trench and Substrate Resistance on the Latchup Robustness in a BiCMOS Silicon Germanium Technology," in Proceedings of the International Reliability Physics Symposium, April 25-27, 2004.
-
(2004)
Proceedings of the International Reliability Physics Symposium
-
-
Voldman, S.1
Watson, A.2
-
38
-
-
0033732439
-
Electrostatic discharge and high current pulse characterization of epitaxial base silicon germanium heterojunction bipolar transistors
-
March
-
S. Voldman, P. Juliano, R. Johnson, N. Schmidt, A. Joseph, S. Furkay, E. Rosenbaum, J. Dunn, D.L. Harame, and B. Meyerson, "Electrostatic Discharge and High Current Pulse Characterization of Epitaxial Base Silicon Germanium Heterojunction Bipolar Transistors," in Proceedings of the International Reliability Physics Symposium, March 2000, pp.310-316.
-
(2000)
Proceedings of the International Reliability Physics Symposium
, pp. 310-316
-
-
Voldman, S.1
Juliano, P.2
Johnson, R.3
Schmidt, N.4
Joseph, A.5
Furkay, S.6
Rosenbaum, E.7
Dunn, J.8
Harame, D.L.9
Meyerson, B.10
-
39
-
-
0002547270
-
Electrostatic discharge characterization of epitaxial base silicon germanium heterojunction bipolar transistors
-
Sept.
-
S. Voldman, N. Schmidt, R. Johnson., L. Lanzerotti, A. Joseph, C. Brennan, J. Dunn, D. Harame, P. Juliano, E. Rosenbaum, and B. Meyerson, "Electrostatic Discharge Characterization of Epitaxial Base Silicon Germanium Heterojunction Bipolar Transistors," in Proceedings of the EOS/ESD Symposium, Sept. 2000, pp. 239-251.
-
(2000)
Proceedings of the EOS/ESD Symposium
, pp. 239-251
-
-
Voldman, S.1
Schmidt, N.2
Johnson, R.3
Lanzerotti, L.4
Joseph, A.5
Brennan, C.6
Dunn, J.7
Harame, D.8
Juliano, P.9
Rosenbaum, E.10
Meyerson, B.11
-
41
-
-
84948974189
-
Silicon germanium hetero-junction bipolar transistor ESD power clamps and the johnson limit
-
Sept. 13
-
S. Voldman, A. Botula, D. Hui, and P. Juliano, "Silicon Germanium Hetero-junction Bipolar Transistor ESD Power Clamps and the Johnson Limit," in Proceedings of the EOS/ESD Symposium, Sept. 13, 2001, pp.326-336.
-
(2001)
Proceedings of the EOS/ESD Symposium
, pp. 326-336
-
-
Voldman, S.1
Botula, A.2
Hui, D.3
Juliano, P.4
-
42
-
-
84948734726
-
MAX) silicon germanium hetero-junction bipolar transistor with carbon incorporation
-
October
-
MAX) Silicon Germanium Hetero-junction Bipolar Transistor with Carbon Incorporation," in Proceedings of the EOS/ESD Symposium, October 2002, pp.52-61.
-
(2002)
Proceedings of the EOS/ESD Symposium
, pp. 52-61
-
-
Voldman, S.1
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