The influence of process and design of subcollectors on the ESD robustness of ESD structures and silicon germanium heterojunction bipolar transistors in a BiCMOS SiGE technology

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2003, Pages 347-356

  Voldman, Steven H ^a   Lanzerotti, Louis ^a   Ronan, Brian ^b   St Onge, S ^a   Dunn, Jim ^a  

^a IBM MICROELECTRONICS   (United States)

^b PRINCETON UNIVERSITY   (United States)

Author keywords

Electrostatic discharge (ESD); Latchup; Silicon Germanium (SiGe); Transmission line pulse (TLP)

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTROSTATIC DEVICES; SEMICONDUCTING SILICON COMPOUNDS;

TRANSMISSION LINE PULSE (TLP);

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 0038649035     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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