A new I/O signal latchup phenomenon in voltage tolerant ESD protection circuits

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2003, Pages 85-91

  Salcedo Suñer, Jorge ^a   Cline, Roger ^a   Duvvury, Charvaka ^a   Cadena Hernandez, Alfonso ^a   Ting, Lary ^a   Schichl, Joe ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

ESD; I O; Latchup; TLP

Indexed keywords

ELECTRIC POTENTIAL; ELECTRIC POWER SYSTEMS; FAILURE ANALYSIS;

SIGNAL LATCHUPS;

FLIP FLOP CIRCUITS;

EID: 0038310272     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. C. Duvvury, R. Rountree, and O. Adams, "Internal Chip ESD Phenomena Beyond the Protection Circuit," IEEE Tran. on Electron Devices, ED-35, pp. 2133-2139, 1988.
2. S. Sinha, H. Swaminathan, G. Kadamati, and C. Duvvury, "An Automated Tool for Detecting ESD Design Errors," EOS/ESD Symp. Proceedings, pp. 208-217, 1998.
3. I-C Lin, C-Y Huang, M-D Ker, S-Y Chuan, L-Y Leu, F-c Chiu, J-C Tseng, "Anomalous Latchup Failure Induced by On-Chip ESD Protection Circuit in a High-Voltage CMOS Product," International Physics of Failure Conference, Singapore, 2002.
4. J. Miller, M. Khazhinsky, and J. Weldon, "Engineering the Cascoded NMOS Output Buffer for Maximum Vtl," EOS/ESD Symp. Proc., pp. 306-317, 2000.
5. W.Anderson, D. Karakauer, "ESD Protection for Mixed-Voltage I/O Using NMOS Transistors Stacked in a Cascoded Configuration," EOS/ESD Symp. Proc., pp. 54-62, 1998.
6. L. M. Ting, C Duwury, O. Trevino, J.Schichl, and T. Diep, "Integration of TLP Analysis for ESD Troubleshooting", Proc. EOS/ESD Symposium., pp. 445-452, 2001.