-
1
-
-
0014617202
-
Radiation induced integrated tircuit latchup
-
NS-16, Tec
-
J.F. Leavy, and R.A. Poll, "Radiation Induced Integrated Tircuit Latchup," IEEE Trans. On Nuclear Science, NS-16, Tec. 1969,pp.96-103.
-
(1969)
IEEE Trans. on Nuclear Science
, pp. 96-103
-
-
Leavy, J.F.1
Poll, R.A.2
-
2
-
-
0014617233
-
Transient radiation response of complementary symmetry tos integrated circuits
-
TS-16, December
-
W.J. Dennehy, A. G. Holmes-Seidle, and W.F. Leipold, "Transient Radiation Response of Complementary Symmetry TOS Integrated Circuits, " IEEE Trans, On Nuclear Science, TS-16, December 1969, pp.114-119.
-
(1969)
IEEE Trans, on Nuclear Science
, pp. 114-119
-
-
Dennehy, W.J.1
Holmes-Seidle, A.G.2
Leipold, W.F.3
-
3
-
-
0015770573
-
Latchup in CMOS integrated tircuits
-
NS-20, Dec
-
B.L. Gregory, and B.D. Shafer, "Latchup in CMOS Integrated Tircuits," IEEE Trans. On Nuclear Science, NS-20, Dec. 1973, pp.293-299.
-
(1973)
IEEE Trans. on Nuclear Science
, pp. 293-299
-
-
Gregory, B.L.1
Shafer, B.D.2
-
6
-
-
0037691091
-
Analysis of latchup prevention in CMOS ic's using epitaxial buried layer process
-
D. B. Estreich, A. Ochoa, and R.W, Dutton, "Analysis of Latchup Prevention in CMOS IC's Using Epitaxial Buried Layer Process," International Electron Device Meeting (IEDM) Technical Digest, 1978,pp.230-234.
-
(1978)
International Electron Device Meeting (IEDM) Technical Digest
, pp. 230-234
-
-
Estreich, D.B.1
Ochoa, A.2
Dutton, R.W.3
-
7
-
-
0038185073
-
The physics and modelling of latchup and CMOS integrated circuits
-
November
-
D-B. Estreich, "The Physics and Modelling of Latchup and CMOS Integrated Circuits," Integrated Circuits Laboratory, November 1980.
-
(1980)
Integrated Circuits Laboratory
-
-
Estreich, D.-B.1
-
8
-
-
0020909950
-
Epitaxial layer enhancement of n-well guard rings for CMOS circuits
-
Dec
-
R. Troutman, "Epitaxial Layer Enhancement of N-Well Guard Rings for CMOS Circuits," IEEE Trans. On Elec. Dev. Letters, Vol ED-4, Dec. 1983, pp.438-440.
-
(1983)
IEEE Trans. on Elec. Dev. Letters
, vol.ED-4
, pp. 438-440
-
-
Troutman, R.1
-
10
-
-
0020891350
-
Latchup immunity against noise pulses in a CMOS double well structure
-
Dec
-
G. Goto, H. Takahashi, and T. Nakamura, "Latchup Immunity Against Noise Pulses in a CMOS Double Well Structure," International Electron Device Meeting (IEDM) Technical Digest, Dec. 1983, pp. 168-171.
-
(1983)
International Electron Device Meeting (IEDM) Technical Digest
, pp. 168-171
-
-
Goto, G.1
Takahashi, H.2
Nakamura, T.3
-
11
-
-
0020879244
-
Comparison of latch-up in p-and n-well CMOS circuits
-
December
-
D. Takacs, J. Harter, E. P. Jacobs, C. Wemer, U. Schwabe et al, "Comparison of Latch-up in P-and N-well CMOS circuits" International Electron Device Meeting (IEDM) Technical Digest, December 1983,pp.159-164.
-
(1983)
International Electron Device Meeting (IEDM) Technical Digest
, pp. 159-164
-
-
Takacs, D.1
Harter, J.2
Jacobs, E.P.3
Wemer, C.4
Schwabe, U.5
-
12
-
-
0021204461
-
A better understanding of CMOS latchup
-
Jan
-
G. Hu, "A Better Understanding of CMOS Latchup," IEEE Trans. Elec. Dev. ED-31, Jan. 1984, pp. 62-67.
-
(1984)
IEEE Trans. Elec. Dev
, vol.ED-31
, pp. 62-67
-
-
Hu, G.1
-
13
-
-
0022757469
-
Transmission line modeling of substrate resistance and CMOS latchup
-
July
-
R. R. Troutman and M.J. Hargrove, "Transmission Line Modeling of Substrate Resistance and CMOS Latchup," IEEE Trans. Elec. Dev., July 1986.
-
(1986)
IEEE Trans. Elec. Dev
-
-
Troutman, R.R.1
Hargrove, M.J.2
-
14
-
-
28744434587
-
Retrograde well and epitaxial thickness optimization for shallow-and deep-trench collar merged isolation and node trench spt cell and CMOS logic technology
-
S. Voldman, M. Marceau, A. Baker, E. Adler, S. Geissler, J. Slinkman, J. Johnson, and M. Paggi, "Retrograde well and epitaxial thickness optimization for shallow-and deep-trench collar merged isolation and node Trench SPT cell and CMOS Logic Technology," International Electron Device Meeting (IEDM) Technical Digest, 1992, pp.811-815.
-
(1992)
International Electron Device Meeting (IEDM) Technical Digest
, pp. 811-815
-
-
Voldman, S.1
Marceau, M.2
Baker, A.3
Adler, E.4
Geissler, S.5
Slinkman, J.6
Johnson, J.7
Paggi, M.8
-
16
-
-
0029405952
-
MeV implants boost device design
-
Nov
-
S. Voldman, "MeV Implants Boost Device Design," IEEE Circuits and Devices, Vol. 11, No. 6, Nov. 1995, pp. 8-16.
-
(1995)
IEEE Circuits and Devices
, vol.11
, Issue.6
, pp. 8-16
-
-
Voldman, S.1
-
17
-
-
0031707249
-
Latchup in cmos," invited talk
-
April
-
M. Hargrove, S. Voldman, J. Brown, K. Duncan, and W. Craig, "Latchup in CMOS," Invited Talk, in Proceedings of the International Reliability Physics Symposium, April 1998, pp.269-278.
-
(1998)
Proceedings of the International Reliability Physics Symposium
, pp. 269-278
-
-
Hargrove, M.1
Voldman, S.2
Brown, J.3
Duncan, K.4
Craig, W.5
-
19
-
-
0038649271
-
A transmission line pulse (tlp) picosecond imaging circuit analysis (pica) methodology for evaluation of esd and latchup
-
May
-
A. Weger, S. Voldman, F. Stellari, P. Song, P. Sanda, and M. McManus, " A Transmission Line Pulse (TLP) Picosecond Imaging Circuit Analysis (PICA) Methodology for Evaluation of ESD and Latchup," Latchup Session, in Proceedings of the International Reliability Physics Symposium, May 2003, pp. 99-104.
-
(2003)
Latchup Session, in Proceedings of the International Reliability Physics Symposium
, pp. 99-104
-
-
Weger, A.1
Voldman, S.2
Stellari, F.3
Song, P.4
Sanda, P.5
McManus, M.6
-
20
-
-
0038310272
-
A new i/o signal latchup phenomenon in voltage tolerance esd protection circuits
-
May
-
J. Salcedo-Suner, R. Cline, C. Duvvury, A. Cadena-Hernandez, L. Ting, and J. SchichI, "A new I/O signal latchup phenomenon in voltage tolerance ESD protection circuits," Tatchup Sesssion, in Proceedings of the International Reliability Physics Symposium, May 2003, pp. 85-92
-
(2003)
Tatchup Sesssion, in Proceedings of the International Reliability Physics Symposium
, pp. 85-92
-
-
Salcedo-Suner, J.1
Cline, R.2
Duvvury, C.3
Cadena-Hernandez, A.4
Ting, L.5
Schichi, J.6
-
21
-
-
0037634701
-
New observance and analysis of various guard ring structures on latchup-hardness by backside photo emission image
-
May
-
S. Liao, C. Niou, W.T.K. Chien, A. Guo, W. Dong, and C. Huang, "New Observance and Analysis of Various Guard Ring Structures on Latchup-Hardness by Backside Photo emission Image," Latchup Session, in Proceedings of the International Reliability Physics Symposium, May 2003, pp .92-99.
-
(2003)
Latchup Session, in Proceedings of the International Reliability Physics Symposium
, pp. 92-99
-
-
Liao, S.1
Niou, C.2
Chien, W.T.K.3
Guo, A.4
Dong, W.5
Huang, C.6
-
22
-
-
3042603747
-
Deep trench guard ring structures and evaluation of the probability of minority carrier escape for esd and latchup in advanced bicmos sige technology
-
National Chiao-Tung University, Hsin-chu City, Taiwan, November 12-13
-
A, Watson, S. Voldman, and T. Larsen, " Deep Trench Guard Ring Structures and Evaluation of the Probability of Minority Carrier Escape for ESD and Latchup in Advanced BiCMOS SiGe Technology," in Proceedings of the Taiwan Electrostatic Discharge Conference, National Chiao-Tung University, Hsin-chu City, Taiwan, November 12-13, 2003, pp. 97-103.
-
(2003)
Proceedings of the Taiwan Electrostatic Discharge Conference
, pp. 97-103
-
-
Watson, A.1
Voldman, S.2
Larsen, T.3
-
23
-
-
3042516253
-
The effect of deep trench isolation, trench isolation, and sub-collector on the electrostatic discharge (esd) robustness of radio frequency (rf) esd stl-bound p+/n-well diodes in a bicmos silicon germanium technology
-
Sept
-
S. Voldman, "The Effect of Deep Trench Isolation, Trench Isolation, and Sub-collector on the Electrostatic Discharge (ESD) Robustness of Radio Frequency (RF) ESD STl-Bound P+/N-well Diodes in a BiCMOS Silicon Germanium Technology," in Proceedings of the 25th EOS/ESD Symposium, Sept. 2003, pp. 214-223 .
-
(2003)
Proceedings of the 25th EOS/ESD Symposium
, pp. 214-223
-
-
Voldman, S.1
-
24
-
-
0037972719
-
Investigation of esd devices in 0.18 um sige bicmos process
-
May
-
S.S. Chen, T.Y. Chen, T. H. Tang, T. L. Hsu, H.C. Tseng, J.K. Chen, and C. H. Chou, " Investigation of ESD devices in 0.18 um SiGe BiCMOS process," in Proceedings of the International Reliability Physics Symposium, May 2003, pp. 357-361.
-
(2003)
Proceedings of the International Reliability Physics Symposium
, pp. 357-361
-
-
Chen, S.S.1
Chen, T.Y.2
Tang, T.H.3
Hsu, T.L.4
Tseng, H.C.5
Chen, J.K.6
Chou, C.H.7
-
25
-
-
0038649035
-
The influence of process and design of sub-collectors on the esd robustness of esd structures and silicon germanium heterojunction bipolar transistors in a bicmos sige technology
-
May
-
S. Voldman, L. Lanzerotti, B. Ronan, S. St Onge, and J. Dunn, "The influence of process and design of sub-collectors on the ESD robustness of ESD structures and silicon germanium heterojunction bipolar transistors in a BiCMOS SiGe technology," in Proceedings of the International Reliability Physics Symposium, May 2003, pp. 347-356.
-
(2003)
Proceedings of the International Reliability Physics Symposium
, pp. 347-356
-
-
Voldman, S.1
Lanzerotti, L.2
Ronan, B.3
St Onge, S.4
Dunn, J.5
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