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Volumn , Issue , 2003, Pages 357-360

Investigation of ESD devices in 0.18-μm SiGe BiCMOS process

Author keywords

[No Author keywords available]

Indexed keywords

ELECTROSTATICS; HETEROJUNCTION BIPOLAR TRANSISTORS; NATURAL FREQUENCIES; SEMICONDUCTING SILICON COMPOUNDS;

EID: 0037972719     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (9)

References (9)
  • 3
    • 0005963032 scopus 로고    scopus 로고
    • Silicon Germanium heterojunction bipolar transistor ESD power clamps and the Johnson limit
    • S. Voldman, A. Botula, D. Hui, and P. Juliano, "Silicon Germanium Heterojunction Bipolar Transistor ESD Power Clamps and the Johnson Limit," in Proc. EOS/ESD Symp., 2001.
    • (2001) Proc. EOS/ESD Symp.
    • Voldman, S.1    Botula, A.2    Hui, D.3    Juliano, P.4
  • 4
    • 0000344253 scopus 로고    scopus 로고
    • Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-μm suicide CMOS process
    • April
    • M. D. Ker and W. Y. Lo, "Design on the Low-Leakage Diode String for Using in the Power-Rail ESD Clamp Circuits in a 0.35-μm Suicide CMOS Process," IEEE Trans. Solid-State Circuits, vol. 35, pp. 601-611, April 2000.
    • (2000) IEEE Trans. Solid-State Circuits , vol.35 , pp. 601-611
    • Ker, M.D.1    Lo, W.Y.2
  • 5
    • 0027883868 scopus 로고
    • Designing on-chip power supply coupling diodes for ESD protection and noise immunity
    • S. Dabral, R. Aslett, and T. Maloney, "Designing on-Chip Power Supply Coupling Diodes for ESD Protection and Noise Immunity," in Proc. EOS/ESD Symp., 1993, pp. 239-249.
    • (1993) Proc. EOS/ESD Symp. , pp. 239-249
    • Dabral, S.1    Aslett, R.2    Maloney, T.3
  • 6
    • 0029476615 scopus 로고
    • Novel clamp circuits for IC power supply protection
    • T. Maloney and S. Dabral, "Novel Clamp Circuits for IC Power Supply Protection," in Proc. EOS/ESD Symp., 1995, pp. 1-12.
    • (1995) Proc. EOS/ESD Symp. , pp. 1-12
    • Maloney, T.1    Dabral, S.2
  • 7
    • 0031641250 scopus 로고    scopus 로고
    • Novel input ESD protection circuit with substrate-triggering technique in a 0.25-μm shallow-trench-isolation CMOS technology
    • M. D. Ker, T. Y. Chen, C. Y. Wu, H. Tang, K. C. Su, and S. W. Sun, "Novel Input ESD Protection Circuit with Substrate-Triggering Technique in a 0.25-μm Shallow-Trench-Isolation CMOS Technology," in IEEE International Symp. on Circuits and Systems, 1998, pp. 212-215.
    • (1998) IEEE International Symp. on Circuits and Systems , pp. 212-215
    • Ker, M.D.1    Chen, T.Y.2    Wu, C.Y.3    Tang, H.4    Su, K.C.5    Sun, S.W.6
  • 8
    • 0000076478 scopus 로고    scopus 로고
    • Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices
    • December
    • T. Y. Chen and M. D. Ker, "Investigation of the Gate-Driven Effect and Substrate-Triggered Effect on ESD Robustness of CMOS Devices," IEEE Trans. Device and Materials Reliability, vol. 1, pp. 190-203, December 2001.
    • (2001) IEEE Trans. Device and Materials Reliability , vol.1 , pp. 190-203
    • Chen, T.Y.1    Ker, M.D.2
  • 9
    • 0032740282 scopus 로고    scopus 로고
    • Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI
    • January
    • M. D. Ker, "Whole-Chip ESD Protection Design with Efficient VDD-to-VSS ESD Clamp Circuits for Submicron CMOS VLSI" IEEE Trans. Electron Devices, vol. 46, pp. 173-183, January 1999.
    • (1999) IEEE Trans. Electron Devices , vol.46 , pp. 173-183
    • Ker, M.D.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.