Autonomic microprocessor execution via self-repairing arrays

IEEE Transactions on Dependable and Secure Computing

Volumn 2, Issue 4, 2005, Pages 297-310

  Bower, Fred A ^a,b,d   Ozev, Sule ^a,c   Sorin, Daniel J ^a,c,e  

^a IEEE   (United States)

^b Duke University   (United States)

^c Duke University   (United States)

^d IBM   (United States)

^e DUKE UNIVERSITY   (United States)

Author keywords

Logic design reliability and testing; Microcomputers; Microprocessors

Indexed keywords

ARRAYS; COMPUTER HARDWARE; COMPUTER SYSTEM RECOVERY; ERROR DETECTION; LOGIC DESIGN; MICROCOMPUTERS;

BACKWARD ERROR RECOVERY (BER); LOGIC DESIGN RELIABILITY AND TESTING; MICROPROCESSOR EXECUTION; SELF-REPAIRING ARRAY STRUCTURE (SRAS);

MICROPROCESSOR CHIPS;

EID: 30344441095     PISSN: 15455971     EISSN: None     Source Type: Journal    
DOI: 10.1109/TDSC.2005.44     Document Type: Article

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