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Volumn , Issue , 2005, Pages 44-46

Geometric programming for circuit optimization

Author keywords

Circuit sizing; Convex optimization; Generalised geometric programming; Geometric programming

Indexed keywords

DYNAMIC PROGRAMMING; INTEGRATED CIRCUITS; OPTIMIZATION; PROBLEM SOLVING;

EID: 29144479306     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1055137.1055148     Document Type: Conference Paper
Times cited : (29)

References (41)
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  • 4
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    • Digital circuit optimization via geometric programming
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    • Boyd, S.1    Kim, S.-J.2    Patil, D.3    Horowitz, M.4
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    • Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
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    • Chu, C.1    Wong, D.2
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    • 0035567587 scopus 로고    scopus 로고
    • VLSI circuit performance optimization by geometric programming
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    • Optimal allocation of local feedback in multistage amplifiers via geometric programming
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    • M. Pattanaik, S. Banerjee, and B. Bahinipati. GP based transistor sizing for optimal design of nanoscale CMOS inverter. In IEEE Conference on Nanotechnology, pages 524-527, Aug. 2003.
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    • Pattanaik, M.1    Banerjee, S.2    Bahinipati, B.3
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    • Kluwer Academic Publishers
    • S. Sapatnekar. Timing. Kluwer Academic Publishers, 2004.
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  • 39
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    • Automated design of operational traiisconductance amplifiers using reversed geometric programming
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    • J. Vanderhaegen and R. Brodersen. Automated design of operational traiisconductance amplifiers using reversed geometric programming. In Proceedings of the 41st IEEE/ACM Design Automation Conference, pages 133-138, San Diego, CA, June 2004.
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    • ORACLE: Optimization with recourse of analog circuits including layout extraction
    • San Diego, CA, June
    • Y. Xu, L. Pileggi, and S. Boyd, ORACLE: Optimization with recourse of analog circuits including layout extraction. In Proceedings of the 41st IEEE/ ACM Design Automation Conference, pages 151-154, San Diego, CA, June 2004.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.