Realization of multiple valued logic and memory by hybrid SETMOS architecture

IEEE Transactions on Nanotechnology

Volumn 4, Issue 6, 2005, Pages 705-714

  Mahapatra, Santanu ^a   Ionescu, Adrian Mihai ^b,c  

^a INDIAN INSTITUTE OF SCIENCE   (India)

^b EPFL   (Switzerland)

^c Institute of Microelectronics and Microsystems   (Switzerland)

Author keywords

Analog hardware description language; Circuit simulation; Compact modeling; Multiple valued logic; Multiple valued memory; Single electron transistors (SETS)

Indexed keywords

ANALOG HARDWARE DESCRIPTION LANGUAGE; CIRCUIT SIMULATION; COMPACT MODELING; MULTIPLE VALUED LOGIC; MULTIPLE VALUED MEMORY; SINGLE-ELECTRON TRANSISTORS (SET);

COULOMB BLOCKADE; FIELD EFFECT TRANSISTORS; LOGIC CIRCUITS; MOS DEVICES; RANDOM ACCESS STORAGE;

CMOS INTEGRATED CIRCUITS;

EID: 28444494460     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2005.858602     Document Type: Article

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