Modelling and analysis of power dissipation in single electron logic

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2002, Pages 323-326

  Mahapatra, Santanu ^a   Ionescu, Adrian M ^a   Banerjee, Kaustav ^b   Declercq, Michel J ^a  

^a EPFL   (Switzerland)

^b University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CHARGE; ELECTRIC INVERTERS; ELECTRIC LOSSES; LEAKAGE CURRENTS; MONTE CARLO METHODS; THERMAL EFFECTS;

SINGLE ELECTRON TRANSISTORS (SET);

TRANSISTORS;

EID: 0036923558     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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3. A. M. Ionescu, M. Declercq, S. Mahapatra, K. Banerjee, J. Gautier, "Few electron devices: towards hybrid CMOS-SET integrated circuits", DAC 2002, pp. 88-93.
4. S. Mahapatra, A.M. Ionescu, K. Banerjee, "A quasi-analytical SET model for few electron circuit simulation", IEEE Electron Dev. Lett., Vol. 23, No. 6, pp. 366-368, 2002.
5. C. Wasshuber, H. Kosina, S. Selberherr, "SIMON-A simulator for single-electron tunnel devices and circuits" IEEE Trans. on CAD, Vol. 16, No. 9, pp. 937-944, 1997.
6. T. Elewa et al., "Performance and physical mechanisms in SIMOX MOS transistors operated at very low temperature", IEEE Trans. on Elec. Dev., Vol. 37, No. 4, pp. 1007-1019, 1990.
7. K. Banerjee and A. Mehrotra, "Power dissipation issues in interconnect performance optimization for sub-180 nm designs", Symp. on VLSI Circuits 2002, pp. 12-15.