Analytical modelling of single electron transistor for hybrid CMOS-SET analog IC design

IEEE Transactions on Electron Devices

Volumn 51, Issue 11, 2004, Pages 1772-1782

  Mahapatra, Santanu ^a   Vaish, Vaibhav ^b   Wasshuber, Christoph ^c   Banerjee, Kaustav ^d   Ionescu, Adrian Mihai ^a  

^a EPFL   (Switzerland)

^b INDIAN INSTITUTE OF TECHNOLOGY KANPUR   (India)

^c TEXAS INSTRUMENTS   (United States)

^d University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; COULOMB BLOCKADE; ELECTRON TUNNELING; HYBRID INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MONTE CARLO METHODS; SEMICONDUCTOR DEVICE MODELS;

ANALOG HARDWARE DESCRIPTION LANGUAGE (AHDL); CMOS NANO CODESIGN; MASTER EQUATION CIRCUIT SIMULATION; ORTHODOX THEORY; SINGLE ELECTRON TRANSISTOR (SET);

TRANSISTORS;

EID: 8144225171     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.837369     Document Type: Article

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