Path based buffer insertion

Proceedings - Design Automation Conference

Volumn , Issue , 2005, Pages 509-514

  Sze, C N ^a   Alpert, Charles J ^b   Hu, Jiang ^a   Shi, Weiping ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

^b IBM   (United States)

Author keywords

Buffer Insertion; Global Routing; Interconnect Synthesis; Layout; Physical Design; Power Minimization

Indexed keywords

ALGORITHMS; COSTS; ESTIMATION;

BUFFER INSERTION; GLOBAL ROUTING; PHYSICAL DESIGN;

VLSI CIRCUITS;

EID: 27944511471     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.2005.193862     Document Type: Conference Paper

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