Prediction of data retention time distribution of DRAM by physics-based statistical simulation

IEEE Transactions on Electron Devices

Volumn 52, Issue 11, 2005, Pages 2422-2429

  Jin, Seonghoon ^a   Yi, Jeong Hyong ^a   Choi, Jae Hoon ^b   Kang, Dae Gwan ^b   Park, Young June ^a   Min, Hong Shick ^a  

^a Seoul National University   (South Korea)

^b Hynix Semiconductor Inc   (South Korea)

Author keywords

Data retention time; Dynamic random access memory (DRAM); Gate induced drain leakage (GIDL); Green's function methods; Leakage currents; Monte Carlo methods; Statistical analysis; Stress (mechanical); Trap assisted tunneling (TAT)

Indexed keywords

COMPUTER SIMULATION; ELECTRON TUNNELING; GREEN'S FUNCTION; INTERPOLATION; LEAKAGE CURRENTS; MONTE CARLO METHODS; POISSON DISTRIBUTION; PROBABILITY DENSITY FUNCTION; STATISTICAL METHODS; STRESSES;

DATA RETENTION TIME DISTRIBUTION; GATE-INDUCED DRAIN LEAKAGE (GIDL); SHOCKLEY-REED-HALL (SRH) PROCESS; STRESS-INDUCED BANDGAP NARROWING (SIBN) EFFECTS; TRAP-ASSISTED TUNNELING (TAT);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 27744468273     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.857185     Document Type: Article

References (29)

1. T. Hamamoto, S. Sugiura, and S. Sawada, "On the retention time distribution of dynamic random access memory (DRAM)," IEEE Trans. Electron Devices, vol. 45, no. 6, pp. 1300-1309, Jun. 1998.
2. J. Y. Kim et al., "The breakthrough in data retention time of DRAM using recess-channel-array transistor (RCAT) for 88 nm feature size and beyond," in Symp. VLSI Tech. Dig., Kyoto, Jun. 2003, pp. 11-12.
3. C. Lee et al., "Enhanced data retention of damascene-finFET DRAM with local channel implantation and (100) fin surface orientation engineering," in IEDM Tech. Dig., Dec. 2004, pp. 61-64.
4. W. Schockley and W. T. Read, "Statics of the recombination of holes and electrons," Phys. Rev., vol. 87, no. 5, pp. 835-842, Jun. 1952.
5. R. N. Hall, "Electron-hole recombination in germanium," Phys. Rev., vol. 87, pp. 387-387, 1952.
6. A. Hiraiwa, M. Ogasawara, N. Natsuaki, Y. Itoh, and H. Iwai, "Statistical modeling of dynamic random access memory data retention characteristics," J. Appl. Phys., vol. 80, no. 5, pp. 3091-3099, Sep. 1996.
7. A. Hiraiwa, M. Ogasawara, N. Natsuaki, Y. Itoh, and H. Iwai, "Field-effect trap-level-distribution model of dynamic random access memory data retention characteristics," J. Appl. Phys., vol. 81, no. 10, pp. 7053-7060, May 1997.
8. A. Hiraiwa, M. Ogasawara N. Natsuaki, Y. Itoh, and H. Iwa, "Local-field-enhancement model of DRAM retention failure," in IEDM Tech. Dig., San Francisco, Dec. 1998, pp. 157-160.
9. S. Ueno, T. Yamashita, H. Oda, S. Komori, Y. Inoue, and T. Nishimura, "Leakage current observation on irregular local pn junctions forming the tail distribution of DRAM retention characteristics, with new test structure," in IEDM Tech. Dig., Dec. 1998, pp. 153-156.
10. K. Yamaguchi, "Temperature dependence of anomalous currents in worst-bit cells in dynamic random-access memories," J. Appl. Phys., vol. 87, no. 11, pp. 8064-8069, Jun. 2000.
11. M. Chang, J. Lin, S. N. Shih, T.-C. Wu, B. Huang, J. Yang, and P.-I. Lee, "Impact of gate-induced drain leakage on retention time distribution of 256 Mbit DRAM with negative wordline bias," IEEE Trans. Electron Devices, vol. 50, no. 4, pp. 1036-1041, Apr. 2003.
12. S. Jin, J.-H. Yi, Y. J. Park, and H. S. Min, "A Monte Carlo method for distribution of standby currents and its application to DRAM retention time," in Int. Conf. Simulation Semiconductor Processes Devices, 2004, pp. 315-318.
13. S. Jin, J.-H. Yi, J. H. Choi, D. G. Kang, Y. J. Park, and H. S. Min, "Modeling of retention time distribution of DRAM cell using a Monte Carlo method," in IEDM Tech. Dig., San Francisco, Dec. 2004, pp. 399-402.
14. F. Bonani, G. Ghione, M. R. Pinto, and R. K. Smith, "An efficient approach to noise analysis through multidimensional physics-based models," IEEE Trans. Electron Devices, vol. 45, no. 1, pp. 261-269, Jan. 1998.
15. F. Bonani and G. Ghione, Noise in Semiconductor Devices. Berlin, Germany: Springer-Verlag, 2001.
16. K. Saino, S. Horiba, S. Uchiyama, Y. Takaishi, M. Takenaka, T. Uchida, and Y. Takada, "Impact of gate-induced drain leakage current on the tail distribution of DRAM retention time," in IEDM Tech. Dig., Dec. 2000, pp. 837-840.
17. K. Saino, K. Okonogi, S. Horiba, M. Sakao, M. Komuro, Y. Takaishi, T. Sakoh, K. Yoshida, and K. Koyama, "Control of trench sidewall stress in bias ECR-CVD oxide-filled STI for enhanced DRAM data retention time," in IEDM Tech. Dig., Dec. 1998, pp. 149-152.
18. D.-C. Kim et al., "Impact of rapid thermal annealing on data retention time for 256 Mb and 1 Gb DRAM technology," in IEDM Tech. Dig., Washington, DC, Dec. 2001, pp. 399-402.
19. G. Vincent, A. Chantre, and D. Bois, "Electric field effect on the thermal emission of traps in semiconductor junctions," J. Appl. Phys., vol. 50, no. 8, pp. 5484-5487, Aug. 1979.
20. G. A. M. Hurkx, D. B. M. Klaassen, and M. P. G. Knuvers, "A new recombination model for device simulation including tunneling," IEEE Trans. Electron Devices, vol. 39, no. 2, pp. 331-338, Feb. 1992.
21. J. J. Wortman, J. R. Hauser, and R. M. Burger, "Effect of mechanical stress on p-n junction device characteristics," J. Appl. Phys., vol. 35, no. 7, pp. 2122-2131, Jul. 1964.
22. P. Smeys, "Geometry and stress effects in scaled integrated circuit isolation technologies," Ph.D. dissertation, Stanford Univ., Stanford, CA, 1996.
23. D. Ha, C. Cho, D. Shin, G.-H. Koh, T.-Y. Chung, and K. Kim, "Anomalous junction leakage current induced by STI dislocations and its impact on dynamic random access memory devices," IEEE Trans. Electron Devices, vol. 46, no. 5, pp. 940-946, May 1999.
24. W. H. Press, S. A. Teukolsky, W. T. Vetterling, and B. P. Flannery, Numerical Recipes in C++. Cambridge, U.K.: Cambridge Univ. Press, 2002.
25. C. Kittel, Introduction to Solid State Physics, 7th ed. New York: Wiley, 1996.
26. J. Bardeen and W. Shockley, "Deformation potentials and mobilities in nonpolar crystals," Phys. Rev., vol. 80, no. 1, pp. 72-80, Oct. 1950.
27. P. M. Fahey, S. R. Mader, S. R. Stiffler, R. L. Mohlet, J. D. Mis, and J. A. Slinkman, "Stress-induced dislocations in silicon integrated circuits," IBM J. Res. Develop., vol. 36, no. 2, pp. 158-182, Mar. 1992.
28. A. Papoulis and S. U. Pillai, Probability, Random Variables, and Stochastic Processes. New York: McGraw-Hill, 2002.
29. J.-H. Yi, S.-K. Park, Y.-J. Park, and H. S. Min, "Numerical analysis of deep-trap behaviors on retention time distribution of DRAM's with negative wordline bias," IEEE Trans. Electron Devices, vol. 52, no. 4, pp. 554-560, Apr. 2005.