Enhanced data retention of damascene-finFET DRAM with local channel implantation and <100> fin surface orientation engineering

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 61-64

  Lee, Chul ^b   Yoon, Jae Man ^b   Lee, Choong Ho ^b   Park, Jong Chul ^a   Kim, Tae Yong ^b   Kang, Hee Soo ^b   Sung, Suk Kang ^b   Cho, Eun Suk ^b   Cho, Hye Jin ^b   Ahn, Young Joon ^b   Park, Donggun ^b   Kim, Kinam ^b   Ryu, Byung I I ^b  

^a Device Research Team   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DATA ACQUISITION; ELECTRIC RESISTANCE; ELECTRON MOBILITY; FABRICATION; FIELD EFFECT TRANSISTORS; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTING SILICON; SURFACE TREATMENT; THIN FILMS; DYNAMIC RANDOM ACCESS STORAGE; FINS (HEAT EXCHANGE); ION IMPLANTATION;

CHANNEL DIRECTIONAL WAFERS (CW); DAMASCENCE; HIGH DENSITY PLASMAS (HDP); LOCAL CHANNEL ION IMPLANTATION (LCI); SHORT CHANNEL EFFECTS (SCE);

DYNAMIC RANDOM ACCESS STORAGE; FINFET;

ARRAY TRANSISTORS; CELL ARRAY; CHANNEL DIRECTIONAL WAFERS; CHANNEL IMPLANTATION; CHANNEL REGION; DATA-RETENTION; FIN SURFACE; FINFETS; LOCAL CHANNEL ION IMPLANTATIONS; SURFACE ORIENTATION;

EID: 21644451805     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. C.H. Lee, et al., "Novel Body Tied FinFET Cell Transistor DRAM with NWL operation for sub 60nm Technology and beyond," VLSI Tech. Dig., p130, 2004.
2. R. Katsumata, et al., "Fin-Array-FET on bulk silicon for sub-100nm Trench Capacitor DRAM," VLSI Tech. Dig., p61, 2003.
3. B. Doris, et al., "A Simplified Hybrid Orientation Technology for High Performance CMOS," VLSI Tech. Dig., P86, 2004.
4. H. Sayama, et al., "Effect of <100> Channel Direction for High Performance SCE Immune pMOSFET with less than 0.15um Gate Length," IEDM, p657, 1999.
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6. S. C. Sun and J. D. Plummer, "Electron Mobility in Inversion and Accumulation Layers on Thermally Oxidized Silicon Surfaces," IEEE J. Solid-State Circuits, p562, 1980.
7. H. J. Cho, et al., "Fin Width Scaling Criteria of Body-Tied FinFET in Sub 50nm Regime," DRC, p209, 2004.