Impact of gate-induced drain leakage on retention time distribution of 256 Mbit DRAM with negative wordline bias

IEEE Transactions on Electron Devices

Volumn 50, Issue 4, 2003, Pages 1036-1041

  Chang, Minchen ^a   Lin, Jengping ^a   Shih, Steven N ^b   Wu, Tieh Chiang ^b   Huang, Brady ^b   Yang, Jen ^b   Lee, Pei Ing ^b  

^a CHANG GUNG UNIVERSITY   (Taiwan)

^b NANYA TECHNOLOGY CORPORATION   (Taiwan)

Author keywords

Gate induced drain leakage (GIDL); Negative wordline; Retention time

Indexed keywords

CAPACITANCE; DIELECTRIC MATERIALS; ELECTRIC POTENTIAL; ELECTRON TUNNELING; INTERFACES (MATERIALS); LEAKAGE CURRENTS; NUMERICAL METHODS;

GATE-INDUCED DRAIN LEAKAGE (GIDL);

GATES (TRANSISTOR);

EID: 0038156171     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.812498     Document Type: Article

References (13)

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