Control of trench sidewall stress in bias ECR-CVD oxide-filled STI for enhanced DRAM data retention time

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1998, Pages 149-152

  Saino, K ^a   Okonogi, K ^a   Horiba, S ^a   Sakao, M ^a   Komuro, M ^a   Takaishi, Y ^a   Sakoh, T ^a   Yoshida, K ^a   Koyama, K ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL VAPOR DEPOSITION; CRYSTAL DEFECTS; LEAKAGE CURRENTS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE TESTING; SEMICONDUCTOR STORAGE; STRAIN; STRESS ANALYSIS;

SHALLOW TRENCH ISOLATION (STI); TRENCH SIDEWALL STRESSES;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0032266921     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)