Numerical analysis of deep-trap behaviors on retention time distribution of DRAMs with negative wordline bias

IEEE Transactions on Electron Devices

Volumn 52, Issue 4, 2005, Pages 554-560

  Yi, Jeong Hyong ^a   Park, Sung Kye ^b   Park, Young June ^a   Min, Hong Shick ^a  

^a Seoul National University   (South Korea)

^b Hynix Semiconductor Inc   (South Korea)

Author keywords

Activation energy; Gate induced drain leakage (GIDL); Negative wordline; Retention time; Tail distribution; Trap assisted tunneling (TAT)

Indexed keywords

ACTIVATION ENERGY; CELLULAR ARRAYS; ELECTRON TRAPS; ELECTRON TUNNELING; FERMI LEVEL; GATES (TRANSISTOR); LEAKAGE CURRENTS; SEMICONDUCTOR DEVICE MODELS; SENSITIVITY ANALYSIS;

GATE-INDUCED DRAIN LEAKAGE; NEGATIVE WORDLINE; RETENTION TIME; TAIL DISTRIBUTION; TRAP-ASSISTED TUNNELING;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 17444431955     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.845151     Document Type: Article

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