메뉴 건너뛰기




Volumn 31, Issue , 2004, Pages 238-249

From sequences of dependent instructions to functions: An approach for improving performance without ILP or speculation

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BENCHMARKING; CACHE MEMORY; COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; DATA PROCESSING; OPTIMIZATION;

EID: 4644280001     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (23)

References (25)
  • 1
    • 0003837824 scopus 로고    scopus 로고
    • October Compaq Computer Corporation
    • Alpha architecture handbook, October 1998. Compaq Computer Corporation.
    • (1998) Alpha Architecture Handbook
  • 2
    • 4344685948 scopus 로고    scopus 로고
    • Virtex-II pro platform FPGAs: Functional description
    • January. Xilinx Corporation
    • Virtex-II pro platform FPGAs: Functional description. Technical Report DS083-2, January 2002. Xilinx Corporation.
    • (2002) Technical Report , vol.DS083-2
  • 3
    • 0003510233 scopus 로고    scopus 로고
    • Evaluating future microprocessors: The SimpleScalar tool set
    • D. Burger, T. M. Austin, and S. Bennett. Evaluating future microprocessors: The SimpleScalar tool set. Technical Report CS-TR-1996-1308, 1996.
    • (1996) Technical Report , vol.CS-TR-1996-1308
    • Burger, D.1    Austin, T.M.2    Bennett, S.3
  • 6
    • 0000227930 scopus 로고    scopus 로고
    • Reconfigurable computing: A survey of systems and software
    • K. Compton and S. Hauck. Reconfigurable computing: a survey of systems and software. ACM Computing Surveys (CSUR), 34(2):171-210, 2002.
    • (2002) ACM Computing Surveys (CSUR) , vol.34 , Issue.2 , pp. 171-210
    • Compton, K.1    Hauck, S.2
  • 14
    • 0035363244 scopus 로고    scopus 로고
    • RePLay: A hardware framework for dynamic optimization
    • June
    • S. J. Patel and S. S. Lumetta. rePLay: A hardware framework for dynamic optimization. IEEE Transactions on Computers, 50(6), June 2001.
    • (2001) IEEE Transactions on Computers , vol.50 , Issue.6
    • Patel, S.J.1    Lumetta, S.S.2
  • 21
    • 0025401087 scopus 로고
    • Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers
    • March
    • G. Sohi. Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers. IEEE Transactions on Computers, 39(3), March 1990.
    • (1990) IEEE Transactions on Computers , vol.39 , Issue.3
    • Sohi, G.1
  • 23
    • 0033703884 scopus 로고    scopus 로고
    • CHIMAERA: A high-performance architecture with a tightly-coupled reconfigurable functional unit
    • Vancouver, British Columbia, June 12-14. IEEE Computer Society and ACM SIGARCH
    • Z. A. Ye, A. Moshovos, S. Hauck, and P. Banerjee. CHIMAERA: A high-performance architecture with a tightly-coupled reconfigurable functional unit. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 225-235, Vancouver, British Columbia, June 12-14, 2000. IEEE Computer Society and ACM SIGARCH.
    • (2000) Proceedings of the 27th Annual International Symposium on Computer Architecture , pp. 225-235
    • Ye, Z.A.1    Moshovos, A.2    Hauck, S.3    Banerjee, P.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.