Instruction generation and regularity extraction for reconfigurable processors

Proceedings of the 2002 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES '02

Volumn , Issue , 2002, Pages 262-269

  Brisk, Philip ^a   Kaplan, Adam ^a   Kastner, Ryan ^a   Sarrafzadeh, Majid ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Control data flow graph; Hardware compiler; Slack; Template

Indexed keywords

CHIP AREAS; CONTROL DATA; DATA-FLOW GRAPHS; EFFECTIVE TOOL; EMBEDDED HARDWARE; HARDWARE COMPILERS; RECONFIGURABLE FABRICS; RECONFIGURABLE PROCESSORS; TEMPLATE GENERATION;

ALGORITHMS; DATA FLOW ANALYSIS; EMBEDDED SYSTEMS; GRAPHIC METHODS; OPTIMIZATION; SYNTHESIS (CHEMICAL);

PROGRAM COMPILERS;

EID: 77952993550     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/581630.581672     Document Type: Conference Paper

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