Evaluation of fault-tolerant designs implemented on SRAM-based FPGAs

Proceedings - IEEE Pacific Rim International Symposium on Dependable Computing

Volumn , Issue , 2004, Pages 327-332

  Asadi, Ghazanfar ^a   Miremadi, Seyed Ghassem ^a   Zarandi, Hamid R ^a   Ejlali, Alireza ^a  

^a SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

COMMERCIAL-OFF-THE-SHELF (COTS); LOGIC ELEMENTS (LE); PROGRAMMABLE LOGIC DEVICES (PLD); SINGLE EVENT UPSETS (SEU);

BENCHMARKING; COSTS; EMBEDDED SYSTEMS; FAULT TOLERANT COMPUTER SYSTEMS; INPUT OUTPUT PROGRAMS; NEUTRONS; SERVERS; STATIC RANDOM ACCESS STORAGE;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 2642572580     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PRDC.2004.1276583     Document Type: Conference Paper

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