FPGA test and coverage

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 599-607

  Toutounchi, Shahin ^a   Lai, Andrew ^a  

^a NONE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONFIGURABLE LOGIC BLOCK; DIGITAL CLOCK MANAGER; GATE LEVEL FAULT GRADING; ITERATIVE LOGIC UNIT;

BUFFER STORAGE; BUILT-IN SELF TEST; COMBINATORIAL CIRCUITS; FAULT TREE ANALYSIS; LOGIC DESIGN; MULTIPLYING CIRCUITS; RANDOM ACCESS STORAGE; SEQUENTIAL CIRCUITS; SHIFT REGISTERS; TABLE LOOKUP;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0036444837     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2002.1041811     Document Type: Article

References (7)

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3. M. Abramovici, C. Stroud, ILA BIST for FPGAs: A Free Lunch with Gourmet Food, 2nd IEEE International On-line testing Workshop, pp 91-95 Biarritz, FRANCE, 1996.
4. Wei Kang Huang, Fred J. Meyer, Xiao-Tao Chen and Fabrizio Lombardi, Testing Configurable LUT-Based FPGAs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp 276-283 Vol. 6, No 2, June 1998
5. Virtex-II Platform FPGA Handbook, Xilinx Inc. Dec. 2000
6. S.M. Trimberger, Field-Programmable Gate Array Technology Kluwer Academic Publishers, 1992
7. A.J. van de Goor, Testing Semiconductor Memories theory & practice pp 153-157 A.J. van de Goor August 2001