A novel fault injection method for system verification based on FPGA boundary scan architecture

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 923-929

  Chakraborty, Tapan J ^a   Chiang, Chen Huan ^a  

^a NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUILT-IN SELF TEST; DESIGN FOR TESTABILITY; FAILURE ANALYSIS; FIELD PROGRAMMABLE GATE ARRAYS; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; PRINTED CIRCUIT BOARDS;

BOUNDARY SCAN REGISTER; FAULT INJECTION METHOD; SYSTEM VERIFICATION; TEST ACCESS PORT CONTROLLER; USER-DEFINED INSTRUCTION;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 0036446181     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. S. Chau. Fault Injection Boundary Scan Design for Verification of Fault Tolerant Systems. In Proceedings IEEE International Test Conference, pages 677-682, 1994.
2. H. Hulvershorn, P. Soong, and S. Adham. Linking Diagnostic Software to Hardware Self Test in Telecom Systems. In Proceedings IEEE International Test Conference, pages 986-993, 1995.
3. IEEE. IEEE Standard Test Access Port and Boundary-Scan Architecture.
4. W. Ke. Backplane Interconnect Test In A Boundary-Scan Environment. In Proceedings IEEE International Test Conference, pages 717-724, 1996.
5. W. Ke. Hybrid Pin Control Using Boundary Scan and Its Applications. In Proceedings Asian Test Symposium, 1996.
6. B. Nadeua-Dostie, H. Hulvershorn, and S. M. Adham. A New Hardware Fault Insertion Scheme for System Diagostics Verification. In Proceedings IEEE International Test Conference, pages 994-1002, 1995.
7. R. M. Sedmak. Boundary-Scan: Beyond Production Test. In Proceedings IEEE International Test Conference, pages 415-420, 1994.
8. L. Whetsel. A Proposed Method of Accessing 1149.1 in a Backplane Environment. In Proceedings IEEE International Test Conference, pages 206-216, 1992.