메뉴 건너뛰기




Volumn , Issue , 2003, Pages 644-649

Switch-level emulation

Author keywords

Emulation; FPGA chips; Gate level models; Switch level models

Indexed keywords

COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS; GATES (TRANSISTOR); LOGIC GATES; MICROPROCESSOR CHIPS; TRANSISTORS;

EID: 0042134689     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775995.775996     Document Type: Conference Paper
Times cited : (2)

References (14)
  • 3
    • 0021377624 scopus 로고
    • A switch-level model and simulator for MOS digital systems
    • Feb
    • Bryant, R.E., A Switch-Level Model and Simulator for MOS Digital Systems, IEEE Transactions on Computers, Vol. C-33, No. 2, pp. 160-177, Feb 1984.
    • (1984) IEEE Transactions on Computers , vol.C-33 , Issue.2 , pp. 160-177
    • Bryant, R.E.1
  • 7
    • 27544463457 scopus 로고
    • FOCUS: An experimental environment for fault sensitivity analysis
    • Dec.
    • Choi, G.S., and Iyer, R.K., FOCUS: An Experimental Environment for Fault Sensitivity Analysis, IEEE Transactions on Computers, vol. 41, no. 12, pp.1515-1526, Dec. 1992.
    • (1992) IEEE Transactions on Computers , vol.41 , Issue.12 , pp. 1515-1526
    • Choi, G.S.1    Iyer, R.K.2
  • 14
    • 0042193272 scopus 로고
    • Verilog hardware descriptor language reference manual (LRM) Draft
    • April
    • Verilog Hardware Descriptor Language Reference Manual (LRM) DRAFT, IEEE-STD 1364, April 1995.
    • (1995) IEEE-STD , vol.1364


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.