On the advantages of serial architectures for low-power reliable computations

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2005, Pages 276-281

  Beiu, V ^a   Aunet, S ^b   Nyathi, J ^a   Rydberg III, R R ^a   Djupdal, A ^c  

^a WASHINGTON STATE UNIVERSITY   (United States)

^b UNIVERSITY OF OSLO   (Norway)

^c NORWEGIAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Norway)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL LEVELS; POWER DELAY; SERIAL ADDERS; SUPPLY VOLTAGES;

COMPUTER SIMULATION; FAULT TOLERANT COMPUTER SYSTEMS; MULTIPLEXING; RELIABILITY; THRESHOLD VOLTAGE;

COMPUTER ARCHITECTURE;

EID: 24944590564     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2005.48     Document Type: Conference Paper

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