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Volumn 3, Issue , 2004, Pages 1983-1988

Reconfigurable subthreshold CMOS perceptron

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN LOGIC; MOORE'S LAW; NEURONS; THERMAL VOLTAGE;

EID: 10844292586     PISSN: 10987576     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IJCNN.2004.1380919     Document Type: Conference Paper
Times cited : (21)

References (17)
  • 1
    • 0141485506 scopus 로고    scopus 로고
    • VLSI implementations of threshold logic - A comprehensive survey
    • Sept.
    • V. Beiu, J. M. Quintana, and M. J. Avedillo, "VLSI Implementations of Threshold Logic - a Comprehensive Survey," IEEE Transactions on Neural Networks, vol. 14, pp. 1217-1243, Sept. 2003.
    • (2003) IEEE Transactions on Neural Networks , vol.14 , pp. 1217-1243
    • Beiu, V.1    Quintana, J.M.2    Avedillo, M.J.3
  • 2
    • 84954088099 scopus 로고
    • An intelligent MOS transistor featuring gate-level weighted sum and threshold operations
    • Washington DC, USA, December
    • T. Shibata, T. Ohmi, "An intelligent MOS transistor featuring gate-level weighted sum and threshold operations," Technical Digest of International Electron Devices Meeting, Washington DC, USA, December, 1991, pp. 919-922.
    • (1991) Technical Digest of International Electron Devices Meeting , pp. 919-922
    • Shibata, T.1    Ohmi, T.2
  • 4
    • 10844288351 scopus 로고
    • "Threshold Gate Circuits Employing Field-Effect Transistors" U. S. Patent 3 715 603, Feb. 6
    • J. B. Lerch, "Threshold Gate Circuits Employing Field-Effect Transistors" U. S. Patent 3 715 603, Feb. 6, 1973.
    • (1973)
    • Lerch, J.B.1
  • 5
    • 0024092691 scopus 로고
    • A symmetric CMOS NOR gate for high-speed applications
    • October
    • M. G. Johnson, "A Symmetric CMOS NOR Gate for High-Speed Applications," IEEE Journal of Solid-State Circuits, vol. 23, pp. 1233-1236, October 1988.
    • (1988) IEEE Journal of Solid-state Circuits , vol.23 , pp. 1233-1236
    • Johnson, M.G.1
  • 10
    • 10844264904 scopus 로고    scopus 로고
    • Multiple-input floating-gate linear threshold element tuned by well potential adjustment
    • Copenhagen, Denmark, November
    • S. Aunet, T. Ytterdal, Y. Berg, T. Sæther, "Multiple-input Floating-Gate Linear Threshold Element Tuned by Well Potential Adjustment, " Proceedings of the 20th IEEE Norchip Conference, Copenhagen, Denmark, November 2002, pp. 220-225.
    • (2002) Proceedings of the 20th IEEE Norchip Conference , pp. 220-225
    • Aunet, S.1    Ytterdal, T.2    Berg, Y.3    Sæther, T.4
  • 12
    • 0028044343 scopus 로고
    • Self-adjusting threshold-voltage scheme (SATS) for low-voltage high-speed operation
    • San Diego, CA, USA, May
    • T. Kobayashi, T. Sakurai, "Self-adjusting Threshold-Voltage Scheme (SATS) for low-voltage high-speed operation," Proceedings of the IEEE Custom Integrated Circuits Conference, San Diego, CA, USA, May 1994, pp. 271-274.
    • (1994) Proceedings of the IEEE Custom Integrated Circuits Conference , pp. 271-274
    • Kobayashi, T.1    Sakurai, T.2
  • 16
    • 0242443318 scopus 로고    scopus 로고
    • Real-time reconfigurable linear threshold elements implemented in floating-gate CMOS
    • Sept.
    • S. Aunet, Y. Berg, T. Sæther, "Real-time reconfigurable linear threshold elements implemented in floating-gate CMOS," IEEE Transactions on Neural Networks, vol. 14, pp. 1244-1256, Sept. 2003.
    • (2003) IEEE Transactions on Neural Networks , vol.14 , pp. 1244-1256
    • Aunet, S.1    Berg, Y.2    Sæther, T.3
  • 17
    • 0000935173 scopus 로고    scopus 로고
    • Deeper sparser nets can be optimal
    • Dec.
    • V. Beiu, H. Makaruk, "Deeper Sparser Nets can be Optimal," Neural Proc. Letters, vol. 8, pp. 201-210, Dec. 1998.
    • (1998) Neural Proc. Letters , vol.8 , pp. 201-210
    • Beiu, V.1    Makaruk, H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.