Substrate-bias optimized 0.18um 2.5GHz 32-bit adder with post-manufacture tunable clock

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)

Volumn 2005, Issue , 2005, Pages 341-344

  Kuo, Qi Wei ^a   Sharma, Vikas ^b   Chen, Charlie Chung Ping ^b  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b University of Wisconsin Madison   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SUBSTRATE-BIAS OPTIMIZATION; TUNABLE CLOCK; TUNABLE DELAY;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; OPTIMIZATION; SUBSTRATES; TUNING;

ADDERS;

EID: 33745440737     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VDAT.2005.1500091     Document Type: Conference Paper

References (11)

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