Neuromorphic CMOL circuits

Proceedings of the IEEE Conference on Nanotechnology

Volumn 1, Issue , 2003, Pages 339-342

  Likharev, K K ^a  

^a STONY BROOK UNIVERSITY   (United States)

Author keywords

CMOS logic circuits; CMOS technology; Fabrication; MOSFETs; Nanoscale devices; Neuromorphics; Self assembly; Single electron devices; Single electron transistors; Very large scale integration

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPLEX NETWORKS; ELECTRON DEVICES; FABRICATION; LOGIC CIRCUITS; MOSFET DEVICES; NANOTECHNOLOGY; PATTERN RECOGNITION; SELF ASSEMBLY; VLSI CIRCUITS;

CMOS LOGIC CIRCUITS; CMOS TECHNOLOGY; MOSFETS; NANOSCALE DEVICE; NEUROMORPHICS; SINGLE-ELECTRON DEVICES;

SINGLE ELECTRON TRANSISTORS;

EID: 84874770577     PISSN: 19449399     EISSN: 19449380     Source Type: Conference Proceeding    
DOI: 10.1109/NANO.2003.1231787     Document Type: Conference Paper

References (16)

1. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, "Device scaling limits of Si MOSFETs and their application dependencies", Proc. IEEE, vol. 89, pp. 259-288, March 2001.
2. K. K. Likharev, "Electronics below 10 nm", in Nano and Giga Challenges in Microelectronics, J. Greer, A. Korkin and J. Labanowski, Eds. Amsterdam: Elsevier, in press; preprint available of the Web at http://rsfq1.physics.sunysb.edu/~likharev/nano/NanoGiga.pdf.
3. K. K. Likharev, "Single-electron devices and their applications", Proc. IEEE, vol. 78, pp. 606-632, April1999.
4. S. P. Gubin et al., "Molecular clusters as building blocks for nanoelectronics: The first demonstration of cluster single-electron tunneling transistor at room temperature", Nanotechnology, vol. 13, pp. 185-194, April 2002.
5. N. B. Zhitenev, H. Meng, and Z. Bao, "Conductance of small molecular junctions", Phys. Rev. Lett., vol. 88, pp. 226801 1-4, June 2002.
6. J. Park et al., "Coulomb blockade and the Kondo effect in single-atom transistors", Nature, vol 417, pp. 725-727, June 2002.
7. C. P. Collier et al., "Electronically configurable molecular-based logic gates", Science, vol. 285, pp. 391-394, July 1999.
8. A. N. Korotkov, "Analysis of integrated single-electron memory operation", J. Appl. Phys., vol. 92, pp. 7291-7295, December 2002.
9. S. Fölling, Ö. Türel, and K. Likharev, "Single-electron latching switches as nanoscale synapses", in Proc. of the 2001 Int. Joint Conf. on Neural Networks. Mount Royal, NJ: Int. Neural Network Society, 2001, pp. 216-221.
10. Ö. Türel and K. K. Likharev, "CrossNets: Possible neuromorphic networks based on nanoscale components", Int. J. of Circuit Theory and Appl., vol. 31, pp. 34-54, January 2003.
11. th Conf. on Molecular-Scale Electronics, New York Acad. Sci., in press.
12. Ö. Türel, I. Muckra, and K. Likharev, "Possible neuromorphic implementation of neuromorphic networks", in Proc. of 2003 Int. Joint Conf. on Neural Networks, in press.
13. J. Hertz, A. Krogh, and R. G. Palmer, Introduction to the Theory of Neural Computation. Cambridge, MA: Perseus, 1991.
14. S. Haykin, Neural Networks. Upper Saddle River, NJ: Prentice Hall, 1999.
15. L. O. Chua and L. Yang, "Cellular neural networks", IEEE Trans. on Circuits and Systems", vol. 35, pp. 1257-1290, October 1988.
16. V. P. Roychowdhury, D. B. Janes, and S. Bandyopadhyay, "Nanoelectronic architecture for Boolean logic", Proc. IEEE, vol. 85, pp. 574-588, April 1997.