The clock distribution of the power4 microprocessor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 144-145+137

  Restle, Phillip J ^a   Carter, Craig A ^a   Eckhardt, James P ^a   Krauter, Byron L ^a   McCredie, Bradley D ^a   Jenkins, Keith A ^a   Weger, Alan J ^a   Mule, Anthony V ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; PHASE LOCKED LOOPS; SILICON ON INSULATOR TECHNOLOGY; TIMING JITTER; TOPOLOGY; TRANSISTORS; VISUALIZATION;

CLOCK DISTRIBUTION; PICOSECOND IMAGING FOR CIRCUIT ANALYSIS (PICA);

MICROPROCESSOR CHIPS;

EID: 0036113803     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A clock distribution method for microprocessors
2. A 1 GHz power4 testchip design