SEU reliability analysis of advanced deep-submicron transistors

IEEE Transactions on Device and Materials Reliability

Volumn 5, Issue 2, 2005, Pages 289-295

  Jain, Palkesh ^a   Vasi, Juzer ^a   Lal, Rakesh K ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

Author keywords

Charge enhancement; Elevated source drain; High ; Lateral asymmetric channel (LAC); Scaling; Short channel effects; Single event upset (SEU); SRAM

Indexed keywords

COMPUTER SIMULATION; DIELECTRIC MATERIALS; INTERFACES (MATERIALS); PERMITTIVITY; RELIABILITY; TRANSISTORS;

CHARGE ENHANCEMENT; ELEVATED SOURCE-DRAIN; HIGH-K; LATERAL ASYMMETRIC CHANNEL (LAC); SCALING; SHORT CHANNEL EFFECTS; SINGLE EVENT UPSET (SEU);

MOSFET DEVICES;

EID: 23844541035     PISSN: 15304388     EISSN: None     Source Type: Journal    
DOI: 10.1109/TDMR.2005.848325     Document Type: Conference Paper

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