Process technique for SEU reliability improvement of deep sub-micron SRAM cell

Solid-State Electronics

Volumn 47, Issue 4, 2003, Pages 661-664

  Saxena, P K ^a   Bhat, N ^a  

^a INDIAN INSTITUTE OF SCIENCE   (India)

Author keywords

Dead layer; Linear energy transfer; Pocket halo; Super steep retrograde channel

Indexed keywords

COMPUTER SIMULATION; ENERGY TRANSFER; POSITIVE IONS; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS;

LINEAR ENERGY TRANSFER (LET);

STATIC RANDOM ACCESS STORAGE;

EID: 0037395712     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(02)00329-5     Document Type: Article

References (6)

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6. Srinivasaiah H.C., Bhat N. Optimization of 0.1 μm NMOS transistor using disposable spacer technique. In: Proceedings of VLSI Design and Test Workshop, 2001. p. 298-303.