Elevated source/drain by sacrificial selective epitaxy for high performance deep submicron CMOS: process window versus complexity

IEEE Transactions on Electron Devices

Volumn 47, Issue 7, 2000, Pages 1484-1491

  Augendre, Emmanuel ^b   Rooyackers, Rita ^b   Caymax, Matty ^b   Vandamme, E P ^a,b   De Keersgieter, An ^b   Perelló, Carles ^b   Van Dievel, Marc ^b   Pochet, Sandrine ^b   Badenes, Gonçal ^b  

^a IEEE

^b IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; INTEGRATED CIRCUIT MANUFACTURE; LEAKAGE CURRENTS; MICROELECTRONIC PROCESSING; SEMICONDUCTING SILICON; SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY;

COST REDUCTION; DEEP SUBMICRON CMOS GENERATIONS; JUNCTION LEAKAGE; PROCESS COMPLEXITY; PROCESS WINDOW; SELECTIVE EPITAXY; SHORT CHANNEL EFFECTS; SILICIDED JUNCTIONS;

CMOS INTEGRATED CIRCUITS;

EID: 0034225959     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.848297     Document Type: Article

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