Detailed analysis of FIBL in MOS transistors with high-k gate dielectrics

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2003-January, Issue , 2003, Pages 99-104

  Mohapatra, Nihar R ^a   Desai, Madhav P ^a   Rao, V Ramgopal ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

Author keywords

Analytical models; Degradation; Dielectric devices; Dielectric materials; Dielectrics and electrical insulation; High K dielectric materials; High K gate dielectrics; Medical simulation; MOSFETs; Physics

Indexed keywords

ANALYTICAL MODELS; DEGRADATION; DESIGN; DIELECTRIC DEVICES; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; FIELD EFFECT TRANSISTORS; GATE DIELECTRICS; MOSFET DEVICES; PERMITTIVITY; PHYSICS; SYSTEMS ANALYSIS; TRANSISTORS;

DIELECTRIC PERMITTIVITIES; FRINGING-INDUCED BARRIER LOWERING; HIGH- K GATE DIELECTRICS; HIGH-K DIELECTRIC MATERIALS; MEDICAL SIMULATIONS; MOSFETS; SHORT-CHANNEL PERFORMANCE; STACKED GATE DIELECTRICS;

DIELECTRIC MATERIALS;

EID: 84941334401     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2003.1183121     Document Type: Conference Paper

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