Channel engineering for analog device design in deep submicron CMOS technology for system on chip applications

IEEE Transactions on Electron Devices

Volumn 49, Issue 9, 2002, Pages 1558-1565

  Deshpande, Hemant V ^a,b,c   Cheng, Baohong ^a,b   Woo, Jason C S ^a,d  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c INTEL CORPORATION   (United States)

^d Resonext Communications   (United States)

Author keywords

Channel engineering; CMOS scaling; MOSFETs; Short channel effects

Indexed keywords

CHANNEL ENGINEERING; DRAIN INDUCED BARRIER LOWERING; SHORT CHANNEL EFFECTS; SINGLE POCKET STRUCTURES; SUPER STEEP RETROGRADE DEVICES; SYSTEM ON CHIP;

COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC FIELD EFFECTS; ELECTRIC RESISTANCE MEASUREMENT; GAIN MEASUREMENT; MOSFET DEVICES; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING; TRANSCONDUCTANCE;

CMOS INTEGRATED CIRCUITS;

EID: 0036712433     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2002.801435     Document Type: Article

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