Low-power system scheduling, synthesis and displays

IEE Proceedings: Computers and Digital Techniques

Volumn 152, Issue 3, 2005, Pages 344-352

  Jha, N K ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; CLIENT SERVER COMPUTER SYSTEMS; CMOS INTEGRATED CIRCUITS; ENERGY UTILIZATION; GRAPH THEORY; GRAPHICAL USER INTERFACES; MICROPROCESSOR CHIPS; OPTIMIZATION; SCHEDULING; VOLTAGE CONTROL;

CMOS TECHNOLOGY; DYNAMIC VOLTAGE SCALING (DVS); LOW-POWER SYSTEM; POWER CONSUMPTION;

POWER ELECTRONICS;

EID: 22944492097     PISSN: 13502387     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ip-cdt:20045067     Document Type: Conference Paper

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