Self-aligned SiGe NPN transistors with 285 GHz f MAX and 207 GHz f T in a manufacturable technology

IEEE Electron Device Letters

Volumn 23, Issue 5, 2002, Pages 258-260

  Jagannathan, B ^a,b   Khater, M ^a,b   Pagette, F ^a,b   Rieh, J S ^a,b   Angell, D ^b   Chen, H ^a,b   Florkey, J ^b   Golan, F ^b   Greenberg, D R ^b   Groves, R ^b   Jeng, S J ^b   Johnson, J ^c   Mengistu, E ^b   Schonenberg, K T ^b   Schnabel, C M ^b   Smith, P ^b   Stricker, A ^c   Ahlgren, D ^b   Freeman, G ^a,b   Stein, K ^b   Subbanna, S ^a,b   more..

^a IEEE   (United States)

^b IBM RESEARCH   (United States)

^c IBM   (United States)

Author keywords

Germanium; Heterojunction bipolar transistors (HBTs); High speed devices; SiGe; Silicon

Indexed keywords

GAIN CUTOFF FREQUENCY; LINEAR CURRENT; MASON UNILATERAL GAIN; PARASITIC RESISTANCE; PINCHED BASE SHEET RESISTANCE;

CAPACITANCE; ELECTRIC BREAKDOWN; ELECTRIC CURRENTS; ELECTRIC RESISTANCE; FREQUENCIES; GAIN MEASUREMENT; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SILICON WAFERS;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 0036575795     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.998869     Document Type: Letter

References (12)

1. T SiGe technology
2. CEO μ 6 V
3. T at 1 mA collector current
4. max 6.7-ps-ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications
5. Ultra high speed SiGe NPN for advanced BiCMOS technology
6. max
7. Prospects for 200 GHz on silicon with SiGe heterojunction bipolar transistors
8. MAX and 6.7-ps ECL
9. A technology simulation methodology for AC-performance optimization of SiGe HBTs
10. max) HBT and ASIC-compatible CMOS using copper interconnect
11. T SiGe heterojunction bipolar transistor with a non-self-aligned (NSA) structure
12. Measurement and modeling of thermal resistance of high speed SiGe heterojunction bipolar transistors