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Volumn , Issue , 2004, Pages 820-829

State variable extraction to reduce problem complexity for ATPG and design validation

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN VALIDATION; FAULT COVERAGES; LOGIC SIMULATION; STATE TRANSITION GRAPHS (STG);

EID: 18144367017     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (6)

References (24)
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  • 4
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    • M. Henftling, H. C. Wittmann and K. J. Antreich; "A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization", Proc. Int'l Conf. Computer-Aided Design, 2002, pp. 304-309.
    • (2002) Proc. Int'l Conf. Computer-aided Design , pp. 304-309
    • Henftling, M.1    Wittmann, H.C.2    Antreich, K.J.3
  • 6
    • 0036734173 scopus 로고    scopus 로고
    • Efficient sequential test generation based on logic simulation
    • S. Sheng and M. S. Hsiao, "Efficient Sequential Test Generation Based on Logic Simulation", IEEE Design and Test of Computers, vol. 19, no. 5, pp. 56-64, 2002
    • (2002) IEEE Design and Test of Computers , vol.19 , Issue.5 , pp. 56-64
    • Sheng, S.1    Hsiao, M.S.2
  • 7
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    • May
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    • Pomeranz, I.1    Reddy, S.M.2
  • 8
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    • (2003) Intl Test Conf. , pp. 281-289
    • Wu, Q.1    Hsiao, M.S.2
  • 9
    • 0028098538 scopus 로고
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  • 14
    • 0034477916 scopus 로고    scopus 로고
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    • C. N. Ip, "Simulation Coverage Enhancement Using Test Stimulus Transformation," Proc. Int'l Conf. CAD, 2000.
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    • Ip, C.N.1
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  • 20
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.