Simulation coverage enhancement using test stimulus transformation

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2000-January, Issue , 2000, Pages 127-133

  Ip, C Norris ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS; BENCHMARKING; BUFFER STORAGE; COMPUTER AIDED LOGIC DESIGN; DECODING; DESIGN FOR TESTABILITY; FORMAL LOGIC;

CACHE COHERENCE; ON THE FLIES; REACHABILITY ANALYSIS; SIMULATION ENVIRONMENT; STATE EXPLORATION; TEST BENCHES; TRANSITION COVERAGE;

COMPUTER AIDED DESIGN; COMPUTER SIMULATION;

CACHE COHERENCE CONTROLLER; FORMAL VERIFICATION; MOTION PICTURE EXPERTS GROUP DECODER; TEST STIMULUS TRANSFORMATION;

EID: 0034477916     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896462     Document Type: Conference Paper

References (13)

1. A. Bouajjani, S. Bensalem, S. Graf, C. Loiseaux, and J. Sifakis. Property preserving abstractions for the verification of concurrent systems. Formal Methods in System Design, 6(1):11-44, 1993.
2. 20states and beyond. IEEE Symp. on Logic in Computer Science, 1990.
3. Mike Benjamin, Daniel Geist, Alan Hartman, Yaron Wolfsthal, Gerard Mas, and Ralph Smeets. A study in coverage-driven test generation. Design Automation Conference, 1999.
4. Malay K. Ganai, Adnan Aziz, and Andreas Kuehlmann. Enhancing simulation with BDDs and ATPG. Design Automation Conference, 1999.
5. Daniel Geist, Monica Farkas, Avner Landver, Yossi Lichtenstein, Shmuel Ur, and Yaron Wolfsthal. Coveragedirected test generation using symbolic techniques. Int. Conf. on Formal Mehtods in Computer-Aided Design, 1996.
6. G. J. Holzmann. An analysis of bitstate hashing. 15th Int. Conf. on Protocol Specification, Testing, and Verification. 1995.
7. Richard C. Ho, C. Han Yang, Mark A. Horowitz, and David L. Dill. Archtecture validation for processors. 22nd Symp. on Computer Architecture, 1995.
8. Daniel Lenoski, James Laudon, Kourosh Gharachorloo, Anoop Gupta, and John Hennessy. The directory-based cache coherence protocol for the DASH multiprocessor. Int. Symp. on Computer Architecture, 1990.
9. D. Moundanos, J.A. Abraham, and Y. V. Hoskote. Abstraction techniques for validation coverage analysis and test generation. IEEE Transaction on Computers, 47(1):2-14, 1998.
10. C. Han Yang and David L. Dill. Validation with guided search of the state space. 35th Design Automation Conference, 1998.
11. Jun Yuan, Jian Shen, Jacob Abraham, and Adnan Aziz. On combining formal and informal verification. Int.l Conf. on Computer-Aided Verification, 1997.
12. Pitro Zafiropulo, Colin H. West, Harry Rudin, D.D. Cowan, and Daniel Brand. Towards analyzing and synthesizing protocols. IEEE Transactions on Communications, 28(4), April 1980.
13. Verilog PLI 1.0, IEEE 1364 Verilog Standard.