Fault simulation based test pattern generator for synchronous sequential circuits

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1999, Pages 260-267

  Guo, Ruifeng ^a   Pomeranz, Irith ^a   Reddy, Sudhakar M ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; OPTIMIZATION; PROBABILITY; SEQUENTIAL CIRCUITS;

FAULT COVERAGES; FAULT SIMULATION BASED TEST PATTERN GENERATOR; SYNCHRONOUS SEQUENTIAL CIRCUITS;

INTEGRATED CIRCUIT TESTING;

EID: 0032660964     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (27)