Deterministic test pattern generation techniques for sequential circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2000-January, Issue , 2000, Pages 538-543

  Hamzaoglu, Ilker ^b   Patel, Janak H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTER AIDED DESIGN; SEQUENTIAL CIRCUITS; TESTING; TIMING CIRCUITS; ALGORITHMS; AUTOMATIC TESTING; C (PROGRAMMING LANGUAGE); COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; OBJECT ORIENTED PROGRAMMING;

AVERAGE CASE PERFORMANCE; BENCHMARK CIRCUIT; DETERMINISTIC TEST PATTERN; FAULT COVERAGES; ITERATIVE LOGIC ARRAYS; SEQUENTIAL CIRCUIT TEST GENERATION; TEST GENERATIONS;

ITERATIVE METHODS; COMPUTER AIDED LOGIC DESIGN;

AUTOMATIC TEST PATTERN GENERATION; DETERMINISTIC TEST PATTERN GENERATION; ITERATIVE LOGIC ARRAYS;

EID: 0034474770     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896528     Document Type: Conference Paper

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