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Volumn , Issue , 2003, Pages 281-289

Efficient Sequential ATPG Based on Partitioned Finite-State-Machine Traversal

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; COMPUTER SIMULATION; FLIP FLOP CIRCUITS; SPECTRUM ANALYSIS;

EID: 0142184816     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (6)

References (16)
  • 2
    • 0027698840 scopus 로고
    • An Efficient Algorithm for Sequential Circuit Test Generation
    • Nov.
    • T. P. Kelsey, K. K. Saluja, and S. Y. Lee, "An Efficient Algorithm for Sequential Circuit Test Generation," IEEE Trans. on Computers, vol. 42, no. 11, pp. 1361-1371, Nov. 1993.
    • (1993) IEEE Trans. on Computers , vol.42 , Issue.11 , pp. 1361-1371
    • Kelsey, T.P.1    Saluja, K.K.2    Lee, S.Y.3
  • 3
    • 0032319387 scopus 로고    scopus 로고
    • New Techniques for Deterministic Test Pattern Generation
    • I. Hamzaoglu and J. H. Patel, "New Techniques for Deterministic Test Pattern Generation," Proc. of VTS, 1998, pp. 446-452
    • (1998) Proc. of VTS , pp. 446-452
    • Hamzaoglu, I.1    Patel, J.H.2
  • 4
    • 0034474770 scopus 로고    scopus 로고
    • Deterministic test pattern generation techniques for sequential circuits
    • I. Hamzaoglu and J. H. Patel, "Deterministic test pattern generation techniques for sequential circuits," Proc. Int'l Conf. Computer-Aided Design, 2000, pp. 538 -543.
    • (2000) Proc. Int'l Conf. Computer-aided Design , pp. 538-543
    • Hamzaoglu, I.1    Patel, J.H.2
  • 5
    • 0029512568 scopus 로고    scopus 로고
    • A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization
    • M. Henftling, H. C. Wittmann and K. J. Antreich; "A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization", Proc. Int'l Conf. Computer-Aided Design, 2002, pp. 304 -309.
    • (2002) Proc. Int'l Conf. Computer-aided Design , pp. 304-309
    • Henftling, M.1    Wittmann, H.C.2    Antreich, K.J.3
  • 7
    • 0036734173 scopus 로고    scopus 로고
    • Efficient Sequential Test Generation Based on Logic Simulation
    • S. Sheng and M. S. Hsiao, "Efficient Sequential Test Generation Based on Logic Simulation", IEEE Design and Test of Computers, vol. 19, no. 5, pp. 56-64, 2002
    • (2002) IEEE Design and Test of Computers , vol.19 , Issue.5 , pp. 56-64
    • Sheng, S.1    Hsiao, M.S.2
  • 9
    • 0031140532 scopus 로고    scopus 로고
    • LOCSTEP: A Logic-Simulation-Based Test Generation Procedure
    • May
    • I. Pomeranz and S. M. Reddy, "LOCSTEP: A Logic-Simulation-Based Test Generation Procedure," IEEE Trans. CAD of Integrated Circuits and Systems, vol. 16, no. 5, May 1997, pp. 544-554.
    • (1997) IEEE Trans. CAD of Integrated Circuits and Systems , vol.16 , Issue.5 , pp. 544-554
    • Pomeranz, I.1    Reddy, S.M.2
  • 10
    • 0028098538 scopus 로고
    • Application of Simple Genetic Algorithms to Sequential Circuit Test Generation
    • E. M. Rudnick et al., "Application of Simple Genetic Algorithms to Sequential Circuit Test Generation," Proc. European Design and Test Conf., 1994, pp. 40-45.
    • (1994) Proc. European Design and Test Conf. , pp. 40-45
    • Rudnick, E.M.1
  • 11
    • 0032660964 scopus 로고    scopus 로고
    • A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits
    • R. Guo, I. Pomeranz, and S. M. Reddy, "A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits," Proc. VLSI Test Symp., 1999, pp. 260-267.
    • (1999) Proc. VLSI Test Symp. , pp. 260-267
    • Guo, R.1    Pomeranz, I.2    Reddy, S.M.3
  • 13
    • 0036444597 scopus 로고    scopus 로고
    • Testing Finite State Machines Based on a Structural Coverage Metric
    • S. Goren and F. J. Ferguson, "Testing Finite State Machines Based on a Structural Coverage Metric", Proc. Int'l Test Conf., 2002, pp. 773-780.
    • (2002) Proc. Int'l Test Conf. , pp. 773-780
    • Goren, S.1    Ferguson, F.J.2
  • 14
    • 84948650869 scopus 로고    scopus 로고
    • Improving Structural FSM Traversal by Constraint-Satisfying Logic Simulation
    • M. Wedler et al., "Improving Structural FSM Traversal by Constraint-Satisfying Logic Simulation", Proc. IEEE Computer Society Annual Symp. VLSI, 2002.
    • (2002) Proc. IEEE Computer Society Annual Symp. VLSI
    • Wedler, M.1
  • 16
    • 0003382839 scopus 로고    scopus 로고
    • ITC 99 benchmark circuits- preliminary results
    • S. Davidson and Panelists, ITC 99 benchmark circuits- preliminary results, Proc. Int'l Test Conf., 1999, pp. 1125.
    • (1999) Proc. Int'l Test Conf. , pp. 1125
    • Davidson, S.1    Panelists2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.