Efficient sequential test generation based on logic simulation

IEEE Design and Test of Computers

Volumn 19, Issue 5, 2002, Pages 56-64

  Sheng, Shuo ^b   Hsiao, Michael S ^a  

^a VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY   (United States)

^b RUTGERS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION; LOGIC SIMULATION;

AUTOMATIC TESTING; COMPUTER SIMULATION; ELECTRIC FAULT CURRENTS; GENETIC ALGORITHMS; SEQUENTIAL CIRCUITS;

INTEGRATED CIRCUIT TESTING;

EID: 0036734173     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2002.1033793     Document Type: Article

References (12)

1. HITEC: A test generation package for sequential circuits
2. CRIS: A test cultivation program for sequential VLSI circuits
3. Application of simple genetic algorithms to sequential circuit test generation
4. Sequential circuit test generation using dynamic state traversal
5. LOCSTEP: A logic-simulation-based test generation procedure
6. A fault simulation based test pattern generator for synchronous sequential circuits
7. Efficient spectral techniques for sequential ATPG
8. Effective safety property checking using simulation-based sequential ATPG
9. Fault simulation based test generation for combinational circuits using dynamically selected subcircuits
10. A fault oriented partial scan design approach
11. Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams