-
1
-
-
0015161126
-
A random and an algorithmic technique for fault detection test generation for sequential circuits
-
Nov.
-
M. A. Breuer, "A random and an algorithmic technique for fault detection test generation for sequential circuits", IEEE Trans. on Computers, vol C-20, No. 11, pp. 1364-1370, Nov. 1971.
-
(1971)
IEEE Trans. on Computers
, vol.C-20
, Issue.11
, pp. 1364-1370
-
-
Breuer, M.A.1
-
3
-
-
0018033699
-
When to use random testing
-
Nov.
-
V. D. Agrawal, "When to use random testing", IEEE Trans. on Computers, vol C-27, No. 11, pp. 1054-1055, Nov. 1978.
-
(1978)
IEEE Trans. on Computers
, vol.C-27
, Issue.11
, pp. 1054-1055
-
-
Agrawal, V.D.1
-
4
-
-
0002569781
-
Fixed-biased pseudorandom built in self test for random pattern resistant circuits
-
M. F. Alshaibi and C. R. Kime, "Fixed-biased pseudorandom built in self test for random pattern resistant circuits", Proc. Intl. Test Conf., 1994, pp. 929-938.
-
(1994)
Proc. Intl. Test Conf.
, pp. 929-938
-
-
Alshaibi, M.F.1
Kime, C.R.2
-
5
-
-
0029250760
-
Structure and technique for pseudo random-based testing of sequential circuits
-
Feb.
-
F. Muradali, T. Nishada, and T. Shimizu, "Structure and technique for pseudo random-based testing of sequential circuits", Journal of Electronic Testing: Theory and Applications, pp. 107-115, Feb. 1995.
-
(1995)
Journal of Electronic Testing: Theory and Applications
, pp. 107-115
-
-
Muradali, F.1
Nishada, T.2
Shimizu, T.3
-
6
-
-
0031353137
-
Vector restoration based static compaction of test sequences for synchronous sequential circuits
-
I. Pomeranz and S. M. Reddy, "Vector restoration based static compaction of test sequences for synchronous sequential circuits", Proc. Intl. Conf. Computer Design, 1997, pp. 360-365.
-
(1997)
Proc. Intl. Conf. Computer Design
, pp. 360-365
-
-
Pomeranz, I.1
Reddy, S.M.2
-
7
-
-
0003140105
-
Procedures for static compaction of test sequences for synchronous sequential circuits based on vector restoration
-
R. Guo, I. Pomeranz, and S. M. Reddy, "Procedures for static compaction of test sequences for synchronous sequential circuits based on vector restoration", Proc. Design, Aut., and Test in Europe, 1998, pp. 583-587.
-
(1998)
Proc. Design, Aut., and Test in Europe
, pp. 583-587
-
-
Guo, R.1
Pomeranz, I.2
Reddy, S.M.3
-
8
-
-
0032660964
-
A fault simulation based test pattern generator for synchronous sequential circuits
-
R. Guo, I. Pomeranz, and S. M. Reddy, "A fault simulation based test pattern generator for synchronous sequential circuits", Proc. VLSI Test Symp., 1999, pp. 260-267.
-
(1999)
Proc. VLSI Test Symp.
, pp. 260-267
-
-
Guo, R.1
Pomeranz, I.2
Reddy, S.M.3
-
9
-
-
0032638542
-
PROPTEST: A property based test pattern generator for sequential circuits using test compaction
-
R. Guo, S. M. Reddy and I. Pomeranz, "PROPTEST: a property based test pattern generator for sequential circuits using test compaction", Proc. Design Aut. Conf., 1999, pp. 653-659.
-
(1999)
Proc. Design Aut. Conf.
, pp. 653-659
-
-
Guo, R.1
Reddy, S.M.2
Pomeranz, I.3
-
11
-
-
0008485464
-
Correlation analysis of compacted test vectors and the use of correlated vectors for test generation
-
March
-
S. Sheng, A. Jain, M. S. Hsiao, and V. D. Agrawal, "Correlation analysis of compacted test vectors and the use of correlated vectors for test generation", IEEE Intl. Test Synthesis Workshop, March, 2000.
-
(2000)
IEEE Intl. Test Synthesis Workshop
-
-
Sheng, S.1
Jain, A.2
Hsiao, M.S.3
Agrawal, V.D.4
-
12
-
-
0003379055
-
Correlation-based test generation for sequential circuits
-
A. Giani, S. Sheng, M. S. Hsiao, and V. D. Agrawal, "Correlation- based test generation for sequential circuits", Proc. IEEE North Atlantic Test Workshop, 2000, pp. 76-83.
-
(2000)
Proc. IEEE North Atlantic Test Workshop
, pp. 76-83
-
-
Giani, A.1
Sheng, S.2
Hsiao, M.S.3
Agrawal, V.D.4
-
13
-
-
0003513556
-
-
Englewood Cliffs, New Jersey: Prentice Hall, Inc.
-
A. V. Oppenheim, R. W. Schafer, J. R. Buck, Discrete-Time Signal Processing. Englewood Cliffs, New Jersey: Prentice Hall, Inc., 1999.
-
(1999)
Discrete-time Signal Processing
-
-
Oppenheim, A.V.1
Schafer, R.W.2
Buck, J.R.3
-
14
-
-
0027072656
-
HITEC: A test generation package for sequential circuits
-
T. M. Niermann and J. H. Patel, "HITEC: A test generation package for sequential circuits", Proc. European Design Aut. Conf., 1991, pp. 214-218.
-
(1991)
Proc. European Design Aut. Conf.
, pp. 214-218
-
-
Niermann, T.M.1
Patel, J.H.2
-
15
-
-
23044521657
-
Dynamic state traversal for sequential circuit test generation
-
July
-
M. S. Hsiao, E. M. Rudnick, and J. H. Patel, "Dynamic state traversal for sequential circuit test generation", ACM Trans. Design Aut. Electronic Systems, vol. 5, no. 3, pp. 548-565, July, 2000.
-
(2000)
ACM Trans. Design Aut. Electronic Systems
, vol.5
, Issue.3
, pp. 548-565
-
-
Hsiao, M.S.1
Rudnick, E.M.2
Patel, J.H.3
-
17
-
-
0003382839
-
ITC'99 benchmark circuits - Preliminary results
-
S. Davidson and Panelists, "ITC'99 benchmark circuits - preliminary results", Proc. Int. Test Conf., 1999, pp. 1125. also at www.cerc.utexas.edu/itc99-benchmarks/bench.html
-
(1999)
Proc. Int. Test Conf.
, pp. 1125
-
-
Davidson, S.1
Panelists2
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