Program slicing for hierarchical test generation

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 237-243

  Vedula, V M ^a   Abraham, J A ^a   Bhadra, J ^b  

^a The University of Texas at Austin   (United States)

^b MOTOROLA INC   (United States)

Author keywords

Application software; Automatic test pattern generation; Circuit testing; Design for testability; Hardware design languages; Logic testing; Manufacturing; Power engineering computing; Test pattern generators; Very large scale integration

Indexed keywords

APPLICATION PROGRAMS; COMPUTATION THEORY; COMPUTER AIDED ENGINEERING; DESIGN; DESIGN FOR TESTABILITY; INTEGRATION TESTING; MANUFACTURE; SOFTWARE TESTING; VLSI CIRCUITS;

CIRCUIT TESTING; HARDWARE DESIGN LANGUAGE; LOGIC TESTING; POWER ENGINEERING COMPUTING; TEST PATTERN GENERATOR;

AUTOMATIC TEST PATTERN GENERATION;

EID: 0142237002     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011144     Document Type: Conference Paper

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