Infrastructure for modular SOC testing

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2004, Pages 671-678

  Marinissen, Erik Jan ^a   Waayers, Tom ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; COMPUTER HARDWARE; IMAGE PROCESSING; INTEGRATED CIRCUITS; OPTIMIZATION; SCHEDULING; TRANSISTORS;

CHIP-LEVEL OPTIMIZATION; DATA VOLUMES; MODULAR TESTING; TEST ACCESS MECHANISMS (TAM);

MICROPROCESSOR CHIPS;

EID: 17044380613     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

1. Erik Jan Marinissen and Yervant Zorian. Challenges in Testing Core-Based System ICs. IEEE Communications Magazine, 37(6):104-109, June 1999.
2. Yervant Zorian, Erik Jan Marinissen, and Sujit Dey. Testing Embedded-Core Based System Chips. In Proceedings IEEE International Test Conference (ITC), pages 130-143, Washington, DC, October 1998.
3. Yervant Zorian, Erik Jan Marinissen, and Sujit Dey. Testing Embedded-Core-Based System Chips. IEEE Computer, 32(6):52-60, June 1999.
4. Erik Jan Marinissen et al. A Structured And Scalable Mechanism for Test Access to Embedded Reusable Cores. In Proceedings IEEE International Test Conference (ITC), pages 284-293, Washington, DC, October 1998.
5. Prab Varma and Sandeep Bhatia. A Structured Test Re-Use Methodology for Core-Based System Chips. In Proceedings IEEE International Test Conference (ITC), pages 294-302, Washington, DC, October 1998.
6. Peter Harrod. Testing Reusable IP - A Case Study. In Proceedings IEEE International Test Conference (ITC), pages 493-498, Atlantic City, NJ, September 1999.
7. Erik Jan Marinissen et al. On IEEE P1500's Standard for Embedded Core Test. Journal of Electronic Testing: Theory and Applications, 18(4/5):365-383, August 2002.
8. Frans Beenker, Karel van Eerdewijk, Robert Gerritsen, Frank Peacock, and Max van der Star. Macro Testing: Unifying IC and Board Test. IEEE Design & Test of Computers, Vol. 3(No. 4):26-32, December 1986.
9. Erik Jan Marinissen. The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs. Journal of Electronic Testing: Theory and Applications, 18(4/5):435-454, August 2002.
10. Frank Bouwman, Steven Oostdijk, Rudi Stans, Ben Bennetts, and Frans Beenker. Macro Testability; The Results of Production Device Applications. In Proceedings IEEE International Test Conference (ITC), pages 232-241, September 1992.
11. Yervant Zorian. Test Requirements for Embedded Core-Based Systems and IEEE P1500. In Proceedings IEEE International Test Conference (ITC), pages 191-199, Washington, DC, November 1997.
12. Rohit Kapur et al. CTL - The Language for Describing Core-Based Test. In Proceedings IEEE International Test Conference (ITC), pages 131-139, Baltimore, MD, October 2001.
13. IEEE Computer Society. IEEE Standard Test Access Port and Boundary-Scan Architecture - IEEE Std. 1149.1-2001. IEEE, New York, July 2001.
14. Joep Aerts and Erik Jan Marinissen. Scan Chain Design for Test Time Reduction in Core-Based ICs. In Proceedings IEEE International Test Conference (ITC), pages 448-457, Washington, DC, October 1998.
15. Robert Arendsen and Maurice Lousberg. Core Based Test for a System on Chip Architecture Framework. In Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), pages 5.1-1-8, Washington, DC, October 1998.
16. Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, and Steven Oostdijk. Test Infrastructure Design for the Nexperia™ Home Platform PNX8550 System Chip. In Proceedings Design, Automation, and Test in Europe (DATE) Designers Forum, pages 108-113, Paris, France, February 2004.
17. Santanu Dutta, Rune Jensen, and Alf Rieckmann. VIPER: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems. IEEE Design & Test of Computers, 18(5):21-31, Sep-Oct 2001.
18. Sandeep Kumar Goel and Erik Jan Marinissen. Effective and Efficient Test Architecture Design for SOCs. In Proceedings IEEE International Test Conference (ITC), pages 529-538, Baltimore, MD, October 2002.
19. Sandeep Kumar Goel and Erik Jan Marinissen. SOC Test Architecture Design for Efficient Utilization of Test Bandwidth. ACM Transactions on Design Automation of Electronic Systems, 8(4):399-429, October 2003.