Embedded DRAM development: Technology, physical design, and application issues

IEEE Design and Test of Computers

Volumn 18, Issue 3, 2001, Pages 7-15

  Keitel Schulz, Doris ^b   Wehn, Norbert ^a  

^a Rheinland Pfälzische Technische Universität Kaiserslautern Landau   (Germany)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CELLULAR ARRAYS; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; EMBEDDED SYSTEMS; LOGIC DESIGN; LOGIC GATES; MICROPROCESSOR CHIPS; RELIABILITY; STORAGE ALLOCATION (COMPUTER); YIELD STRESS;

EMBEDDED DRAM; MEMORY BANDWIDTH; SYSTEM ON CHIP;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0035339227     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.922799     Document Type: Article

References (9)

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2. O. Kimura (moderator), "DRAM + Logic Integration: Which Architecture and Fabrication Process," Proc. Int'l. Solid State Circuits Conf., Digest of Technical Papers, vol. 40, Feb. 1997.
3. Infineon Technology homepage, 2000; http://www.infineon.com/edram.
4. B. Prince, High Performance Memories, John Wiley & Sons, New York, 1996.
5. H. Ikeda and H. Inukai, "High-Speed DRAM Architecture Development," IEEE J. Solid-State Circuits, vol. 34, May 1999, pp. 685-692.
6. JEDEC Solid State Engineering Council, 2001; http://www.jedec.org.
7. S. Iyer and H. Kalter, "Embedded DRAM Technology: Opportunities and Challenges," IEEE Spectrum, Apr. 1999, pp. 56-64.
8. D. Patterson, et al., "Intelligent RAM (IRAM): Chips that Remember and Compute," Proc. Int'l Solid State Circuits Conf., Digest of Technical Papers, vol. 40, Feb. 1997, pp. 224-225.
9. G. Pomicher, "A DRAM Bedfellow for Graphics Controllers," IEEE Spectrum, Apr. 1999, p. 60.