Hierarchical whitespace allocation in top-down placement

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 11, 2003, Pages 1550-1556

  Caldwell, Andrew E ^a   Kahng, Andrew B ^a,b   Markov, Igor L ^a,c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c University of Michigan   (United States)

Author keywords

Algorithms; Design automation; Integrated circuit layout

Indexed keywords

CALCULATIONS; COMPUTATIONAL METHODS; ITERATIVE METHODS; MATHEMATICAL MODELS; RECURSIVE FUNCTIONS; SIMULATED ANNEALING; THEOREM PROVING;

DESIGN AUTOMATION; ITERATIVE PARTITIONER; WHITESPACE ALLOCATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0242636372     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.818375     Document Type: Article

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